NCA&T COMP 375 - Machine Language (12 pages)

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Machine Language



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Machine Language

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Pages:
12
School:
North Carolina A&T State University
Course:
Comp 375 - Computer Architecture and Organization
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9 16 2008 Bunch of Bytes Machine Language Machine language is binary codes that the computer executes The computer fetches the instructions from memory and executes them COMP375 Computer Architecture and Organization Machine language for a square root program Assembler and Machine Instruction Format Assembler language is the easy way to write machine hi llanguage Each line of an assembler program generates one machine language instruction The assembler allows you to use variable names instead of numerical addresses and instruction mnemonics instead of numerical operation codes 8b 89 7d f8 45 45 f8 75 e0 f8 03 e2 89 8b 45 8b 45 f8 89 45 ec 8b 45 ec 45 e0 ba 00 00 00 00 f7 f8 d1 f8 89 45 ec 3b 45 f4 The general format for a machine language i t ti is instruction i Op code Operands The operands can be a memory address address a register or a value 1 9 16 2008 Op codes Data Location Each assembler instruction represents a numerical machine language opcode add cmp dec idiv jmp push sar 05 3B FF 7F 39 68 D0 Intel Assembler The Intel assembler allows you to use one mnemonic for different op codes There are several versions of the add instruction based on the size of the operands The assembler picks the correct op code Opcode Instruction 04 ib ADD AL imm8 05 iw ADD AX imm16 05 id ADD EAX imm32 80 0 ib ADD r m8 imm8 81 0 iwADD r m16 imm16 81 0 id ADD r m32 imm32 83 0 ib ADD r m16 imm8 83 0 ib ADD r m32 imm8 00 r ADD r m8 r8 01 r ADD r m16 r16 01 r ADD r m32 r32 02 r ADD r8 r m8 03 r ADD r16 r m16 03 r ADD r32 r m32 Register The data is in a CPU register Memory The data is in a location in RAM Immediate The data is part of the instruction Immediate data items are read only Mnemonic to Op Code Mapping Description ADD imm8 to AL ADD imm16 to AX ADD imm32 to EAX ADD imm8 to r m8 ADD imm16 to r m16 ADD imm32 to r m32 ADD sign extended ADD sign extended i ADD r8 to r m8 ADD r16 to r m16 ADD r32 to r m32 ADD r m8 to r8 ADD r m16 to r16 ADD r m32 to r32 Intel assembler uses the same mnemonic for th machine the hi llanguage iinstruction t ti tto Move a byte from memory to a register Move a byte from a register to memory The Intel mov instruction generates different machine language op codes depending upon the size of the operands 2 9 16 2008 No operand instructions Number of Operands In addition to the op code the instruction might i ht contain t i zero one two t or th three operands Different architectures use different number of operands A single architecture may have instructions with differing number of operands Some instructions do not require any operands The data affected is implied in the instruction RET Return from function HLT Halt CPUID Get details about the CPU LAHF Load Status Flags into AH Reg Op code One Operand Instructions Some unary operations require only one operand d inc jmp al increment the al register address jump to the address Op code register Op code address Two Operand Instructions Many instructions act on two operands Most math instructions use two operands and return the results in one of them add add imul al varname bl al eax varname Op code register Op code reg1 address reg2 3 9 16 2008 Three Operand Instructions Additional Instruction Fields Some machines support three operands Intel Pentium does not Most MIPS instructions use three operands Most architectures support an addressing mode that combines an address field in the instruction and the contents of a register add Op code reg1 R1 R2 R3 reg2 reg2 add R3 addr R7 This instruction adds the contents of register R3 with the memory location whose address is the sum off the h address dd field f ld and d R7 Op code Variable or Fixed Length Some architectures use variable length i t ti instructions IInstructions t ti with ith more operands d or memory addresses are longer saves memory Some architectures always use the same length instruction easier to find the beginning of instructions instructions are in aligned words reg1 Index reg address Assembled Code addr 004a 004d 0050 0053 machine 8b 45 e0 89 45 f8 89 45 ec 8b 45 ec 0056 0059 005c 0061 0064 0067 0069 006c 006f 0071 89 8b ba f7 03 d1 89 3b 75 8b 45 45 00 7d 45 f8 45 45 e2 f4 f8 e0 00 f8 f8 ec f8 mov mov mov mov again mov mov 00 00 mov idiv add dd sar mov cmp jne mov assembler eax number ebp good ebp eax better ebp eax eax better ebp good ebp eax eax number ebp edx 0 good ebp eax good ebp d b eax 1 better ebp eax eax good ebp SHORT again esi esp 4 9 16 2008 Questions about the code What does SHORT mean after the jne What is the displacement of the jne Example Machine Language Assume each instruction of this imaginary computer is 32 bits in length 8 opcode 4 reg label mnemonic 4 index reg 16 bits address reg address index reg Assembler language format Machine Language Program 00 04 08 0C 10 14 18 1C 20 LOAD R1 y DIV R1 z ADD R1 five STORE R1 x RET x res y res z res 00000005 five 5 01100018 2110001C 05100020 02100014 47000000 World of Numbers The opcodes are numbers The address is a number The register field is a number 8 4 4 16 bits opcode reg index reg g 10100101 0011 0000 Add R3 no indexing address 000000001011010 xyz 5 9 16 2008 What are the Instructions Disassembling Opcodes Any bunch of bits in memory can be considered a program Most random bits may not produce a logical program and may generate errors due to bad opcodes or addressing errors A disassembler is a program that interprets the values in memory as instructions Some software asks not to be disassembled Add Subtract Multiply Divide Load Store JumpEql Jump 0 1 2 3 4 5 6 7 opcode register index register memory address 3 4 4 21 Instruction Formats 1 2 3 4 5 6 Load and Store opcode unused reg 1 reg 2 reg 3 3 1 4 4 4 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 Add Sub Mult and Divide 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 …


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