9/16/20081Machine LanguageMachine LanguageCOMP375Computer Architecture and OrganizationBunch of Bytes• Machine language is binary codes that the computer executes.• The computer fetches the instructions from memory and executes them.Machine language for a square root program8b 45 e0 89 45 f8 89 45 ec 8b 45 ec 89 45 f8 8b 45 e0 ba 00 00 00 00 f7 7d f8 03 45 f8 d1 f8 89 45 ec 3b 45 f8 75 e2 8b f4Assembler and Machine• Assembler language is the easy way to write hi lmachine language.• Each line of an assembler program generates one machine language instruction.• The assembler allows you to use variable names instead of numerical addresses andnames instead of numerical addresses and instruction mnemonics instead of numerical operation codes.Instruction Format• The general format for a machine language it ti iinstruction isOp code OperandsThe operands can be a memory address aThe operands can be a memory address, a register or a value.9/16/20082Op codes• Each assembler instruction represents a numerical machine language opcode.numerical machine language opcode.add 05cmp 3Bdec FFidiv 7Fjmp 39push 68sar D0Data Location• Register –The data is in a CPU register.• Memory–The data is in a location in RAM• Immediate –The data is part of the instruction. Immediate data items are read‐only. Intel Assembler• The Intel assembler allows you to use one mnemonic forOpcode Instruction Description04 ib ADD AL,imm8 ADD imm8 toALone mnemonic for different op codes.• There are several versions of the add instruction based on 05 iw ADD AX,imm16 ADD imm16 to AX05 id ADD EAX,imm32 ADD imm32 to EAX80 /0 ib ADD r/m8,imm8 ADD imm8 to r/m881 /0 iwADD r/m16,imm16 ADD imm16 to r/m1681 /0 idADD r/m32,imm32 ADD imm32 to r/m3283 /0 ibADD r/m16,imm8 ADD sign-extended83 /0 ibADD r/m32,imm8 ADD sign-extended i00 /r ADD r/m8,r8 ADD r8 to r/m801 /r ADD r/m16,r16 ADD r16 to r/m1601 /r ADD r/m32,r32 ADD r32 to r/m3202 /rADDr8,r/m8 ADD r/m8tor8the size of the operands. The assembler picks the correct op code.,03 /r ADD r16,r/m16 ADD r/m16 to r1603 /r ADD r32,r/m32 ADD r/m32 to r32Mnemonic to Op Code Mapping• Intel assembler uses the same mnemonic for th hi l it ti tthe machine language instruction to:– Move a byte from memory to a register– Move a byte from a register to memory• The Intel mov instruction generates different machine language op codes depending uponmachine language op codes depending upon the size of the operands.9/16/20083Number of Operands• In addition to the op code, the instruction iht ti t thmight contain zero, one, two or three operands.• Different architectures use different number of operands.•A single architecture may have instructionsA single architecture may have instructions with differing number of operands.No operand instructions• Some instructions do not require any operands. The data affected is implied in the instruction.• RET —Return from function• HLT —Halt• CPUID —Get details about the CPU•LAHF—Load Status Flags into AH Reg•LAHF —Load Status Flags into AH RegOp codeOne Operand Instructions• Some unary operations require only one doperandinc al ‐ increment the al registerjmp address –jump to the addressOp code registerOp code addressTwo Operand Instructions• Many instructions act on two operands• Most math instructions use two operands and return the results in one of them.• add al,varname• add bl,al• imul eax, varname,Op code register addressOp code reg1 reg29/16/20084Three Operand Instructions• Some machines support three operands (Intel Pentium does not).• Most MIPS instructions use three operandsadd R1,R2,R3Op code reg1 reg2 reg2Additional Instruction Fields• Most architectures support an addressing mode that combines an address field in the instruction and the contents of a registerand the contents of a registeradd R3,addr[R7]• This instruction adds the contents of register R3 with the memory location whose address is the f h dd fld dsum of the address field and R7.Op code reg1Index regaddressVariable or Fixed Length• Some architectures use variable length it ti It ti ith dinstructions. Instructions with more operands or memory addresses are longer.– saves memory• Some architectures always use the same length instruction.length instruction.– easier to find the beginning of instructions– instructions are in aligned wordsAssembled Codeaddr machine assembler004a 8b 45 e0 mov eax, number[ebp]004d 89 45 f8 mov good[ebp], eax0050 89 45 ec movbetter[ebp], eax0053 8b 45 ec mov eax, better[ebp]again:0056 89 45 f8 mov good[ebp], eax0059 8b 45 e0 mov eax, number[ebp]005c ba 00 00 00 00 mov edx, 00061 f7 7d f8 idiv good[ebp]006403 45 f8ddd[ b ]006403 45 f8addeax, good[ebp]0067 d1 f8 sar eax, 10069 89 45 ec mov better[ebp], eax006c 3b 45 f8 cmp eax, good[ebp]006f 75 e2 jne SHORT again 0071 8b f4 mov esi, esp9/16/20085Questions about the code• What does SHORT mean after the jne ?• What is the displacement of the jne ?Example Machine Language• Assume each instruction of this imaginary computer is 32 bits in lengthcomputer is 32 bits in length8 4 4 16 bitsopcode reg indexregaddresslabel: mnemonic reg, address[index reg]Assembler language formatMachine Language Program00 01100018 LOAD R1, y04 2110001C DIV R1, z08 05100020 ADD R1, five0C 02100014 STORE R1, x10 47000000 RET14xres14xres18 yres1C zres20 00000005 five +5World of Numbers• The opcodes are numbers•The address is a number•The address is a number• The register field is a number8 4 4 16 bitsopcode reg indexregaddressg10100101 0011 0000 000000001011010Add R3, [no indexing] xyz9/16/20086Disassembling• Any bunch of bits in memory can be considered a program.• Most random bits may not produce a logical program and may generate errors due to bad opcodes or addressing errors.•A disassembler is a program that interprets theA disassembler is a program that interprets the values in memory as instructions.• Some software asks not to be disassembledWhat are the Instructions?Add Subtract Multiply Divide Load Store JumpEql Jump01234567OpcodesInstruction Formats11111111112222222222333opcode register index registermemory address34 4 21opcodeunusedreg 1 reg 2 reg 331444Load and StoreAdd, Sub, Mult and DivideInstruction