1 21Gate Array Big Picture 22Gate Array Little Picture2San Jose State University CMOS Gate Array Senior Design Project EE198B Submitted to Professor Dr. David Parent College Of Engineering Submitted By Paul Weil Meeta Roy Nancy Ashley Byron Ogada San Jose, California May 20th, 20033Chapter 1: The Basis of the Gate Array................................................................................................................................................ 5 Chapter 2: Gate Array Design............................................................................................................................................................... 6 Chapter 3: Methodology........................................................................................................................................................................ 7 Chapter 4: Advantages and Disadvantages of the Gate Array ............................................................................................................. 8 Chapter 5: Tutorial................................................................................................................................................................................ 9 Gate Array Design Flow ................................................................................................................................................................... 9 Gate Array Design Flow Overview ................................................................................................................................................ 10 Design Specifications.................................................................................................................................................................... 10 Figure 1: Philips 4-bit ALU Schematic...................................................................................................................................... 10 Schematic Capture......................................................................................................................................................................... 11 Stick Diagram/Metal1 Diagram..................................................................................................................................................... 11 Metal1 Gate Array Cell Implementation ....................................................................................................................................... 11 Gate Array Implementation........................................................................................................................................................... 11 Design Specifications....................................................................................................................................................................... 12 Schematic Capture.......................................................................................................................................................................... 13 Figure 2: Create Library ............................................................................................................................................................ 13 Figure 3: Cell View................................................................................................................................................................... 14 Figure 4: And2 Gate Schematic................................................................................................................................................. 14 Figure 5: Symbol Creation......................................................................................................................................................... 15 Figure 6:Created Symbol of and2 gate ..................................................................................................................................... 15 Figure 7:Affirma Analog Environment...................................................................................................................................... 16 Figure 8:And2 Test bench ......................................................................................................................................................... 16 Figure 9:Output Waveform Verifying And2 output Logic......................................................................................................... 17 Stick Diagram/Metal1 Diagram ..................................................................................................................................................... 18 Figure 10: And2 Stick Diagram Example.................................................................................................................................. 18 Metal1 Gate Array Cell Implementation....................................................................................................................................... 18 Figure 11:Library Manager Showing Gate Array Individual Cells............................................................................................ 19 Figure 12:AOI 25 cell................................................................................................................................................................ 20 Figure 13:AOI small cell ........................................................................................................................................................... 20 Figure 14: AOI half-cell ............................................................................................................................................................ 21 Figure 15: AOI main-cell .......................................................................................................................................................... 21 Figure 16:Clk AOI..................................................................................................................................................................... 22 Figure 17: AOI cell used to Implement And2 Gat..................................................................................................................... 22 Figure 17: And2 layout (after Metal1 has been drawn).............................................................................................................. 23 Figure 18: DRC