EE 198B SPRING 2004 PHASE-LOCKED LOOP DESIGN ADVISOR PROFESSOR DAVID PARENT DESIGN TEAM MEMBERS LANA DAM THANH LAM ALFREDO MENDOZA JR.1 TABLE OF CONTENTS CHAPTER 1: PROJECT OVERVIEW ..................................................................... 2 CHAPTER 2: PLL DESIGN....................................................................................... 3 CHAPTER 3: PLL SCHEMATICS AND LAYOUTS................................................ 6 CHAPTER 4: SIMULATIONS................................................................................. 17 CHAPTER 5: PLL TESTING AND RESULTS........................................................ 20 CHAPTER 6: COMPARISON OF PREVIOUS SJSU PLL GROUP AND CURRENT PLL PROJECT....................................................................................... 27 CHAPTER 7: CONCLUSION.................................................................................. 28 APPENDIX A ............................................................................................................. 29 REFERENCE ............................................................................................................. 372 CHAPTER 1: PROJECT OVERVIEW The primary purpose of this senior design project is to create a functional phase-locked loop (PLL) that can operate up to a frequency of 200 MHz. The PLL project consists of three general stages: design using the CADENCE tool, MOSIS for fabrication, and circuit testing using the logic analyzer. For this project, the AMI06 process is used with a 0.5•m technology. PLL is a circuit that synchronizes a reference (input) signal and feedback from its VCO (PLL output) so that the signal and feedback can operate at the same frequency. In typical situations, both of the signals have some type of difference prior to the synchronization process. The time it takes the PLL to synchronize both signals into the same frequency and phase is referred to as “lock time.” The main objective of the PLL is to obtain a locked state at a reasonable amount of lock time. Due to its characteristics, PLL is used for communication systems and other circuits that require a clock recovery circuit, frequency multiplier, and data synchronization.3 CHAPTER 2: PLL DESIGN Figure 1: PLL Component Block Diagram As shown in Figure 1 above, the PLL system is composed of five main components: the Phase/Frequency Detector (PFD), Charge Pump, Loop Filter, Voltage-Controlled Oscillator, and Divider. PHASE/FREQUENCY DETECTOR (PFD) The primary purpose of the PFD is to simply measure the difference in phase and frequency between both signals and produce an output that is proportional to the difference. Since the objective of the PLL is to ensure that the feedback signal is equal to the Reference Signal, the PFD commands the rest of the PLL to either lower or raise the frequency coming out of the voltage controlled oscillator (VCO). This is accomplished by either using its up or down output. Signals from the up output instruct the VCO to increase the frequency and/or phase while signals from the down output performs the opposite. Since this PLL project consists of a Charge Pump and a loop filter, the PFD used is actually a charge pump phase frequency detector (CPPFD). Although there are other PFD designs such as the XORPFD, the CPPFD was better suited for this PLL project, and it also consumes less area. One of the drawbacks to the CPPFD is that it is sensitive to capacitances on its output. The PFD is composed of two D flip flops, one AND gate, and one inverter. CHARGE PUMP The Up and Down output of the PFD is tied to the Charge Pump which is composed of a simple mirror circuit. The Charge Pump basically manipulates the amount of charge on the filter’s capacitors depending on the signals from the up and down of the PFD. If the Reference input of the PLL leads the incoming feedback loop, the up output of the PFD will signal the Charge Pump to add charge into the capacitors. The reverse situation occurs when the Reference input lags the incoming feedback loop.4 LOOP FILTER The Loop Filter is a passive loop filter composed of two capacitors and one resistor. The filter outputs a voltage that informs the VCO to either increase or decrease its output frequency. Its voltage output is proportional to the charge of the capacitors. For this design an extra capacitor was added in parallel to the original capacitor and resistor. This additional capacitor helps with the reduction of incoming noise from the previous components and helps with the reduction of lock time. VOLTAGE CONTROLLED OSCILLATOR Voltage Controlled Oscillators is the main component that produces the necessary frequency output of the PLL. Depending on the input from the other PLL components, the VCO creates a frequency that matches the Reference Signal. For this project, a current starved VCO was chosen due to its simple design and area usage. The current starved VCO has a similar design as a basic ring oscillator, has no capacitors or resistors, and is mainly composed of transistors. Other VCO designs such as source-coupled oscillators use capacitors and resistors that can take up a lot of area. DIVIDER The basic function of the Divider, which is a part of the feedback loop, is to reduce the frequency from the VCO into a value that can be comparable to the Reference Signal. The Divider is very useful since it can make the PLL operate at a higher frequency depending on how much it divides the feedback loop. In this design, a chain of D flip flops were used to create a divider. The amount the Divider divides by depends on the equation “2n = divide by” where n is the amount of D flip flops used. To meet the project’s requirements, a divide by 16 was used. (4 D flip flops) DESIGN SPECIFICATION Name Specification Input signal frequency 10 MHz - 20 MHz Input signal voltage 5V Center voltage of VCO 2.45V Output frequency of the VCO 160 MHz - 320 MHz VSS 0V VDD 5V5 PLL Chip Pin List and Features Features: • Input Rate: 10-20MHz • Operating Rate: 160-320 MHz • 40 Pin DIP Package • 5V Supply • TTL Compatible Logic Pins Figure 2: Pin Layout DESIGN LIMITATION AND TRADEOFF The limitation of our design was due to the padframe. The padframe has a maximum I/O frequency of 25 MHz. To solve this