Section 7.1 − Storage Components Page 1 of 87. Storage Components7.1 RegistersI3I2I1I0Q3QDClk33QDClk22QDClk11QDClk00Q2Q1Q0Clk4-bit registerClkClearPresetI3Q3ClearQDClk3PresetClear3I2Q2ClearQDClk2PresetClear2I1Q1ClearQDClk1PresetClear1I0Q0ClearQDClk0PresetClear04-bit register with preset and clearClkI3Q3QDClk3301syI2Q2QDClk2201syI1Q1QDClk1101syI0Q0QDClk0001syLoad4-bit register with parallel loadSection 7.1 − Storage Components Page 2 of 87.2 Shift RegistersClkILQ3QDClk3301syQ2QDClk2201syQ1QDClk1101syQ0QDClk0001syShift4-bit serial-in / parallel-out shift-right registerILQ302s1y13s0QQ'DClk330I3Q202s1y13s0QQ'DClk220I2Q102s1y13s0QQ'DClk110I1Q002s1y13s0QQ'DClk000I0S0S1ClkIR4-bit shift left/right register with parallel load7.3 CountersClkC4ClearQDClk33HAClearQ3QDClk22HAClearQ2QDClk33HAClearQ1C3C2C1EQDClk00HAClearQ0C0Carry4-bit binary counterS1 S0Operations00 no change01 load input10 shift left11 shift rightQiCiCi+1Di0000010110011110Half Adder (HA)EOperations0 no change1 countSection 7.1 − Storage Components Page 3 of 84-bit up/down binary counter4-bit up/down counter with parallel load)())('()()('''''''''1CQCQDDCQDCQDCDQCDQCQDCQDDCDQCQDCiiiiiiiiiiiiiiiii⊕=⊕+=⊕+⊕=+++=+=+UDHASCi+1DiQiQ'iCiDD'ClkClearECarryQ3Q2Q1Q0DQQ'DClk333ClearUDHASQQ'DClk222ClearUDHASQQ'DClk111ClearUDHASQQ'DClk000ClearUDHASClkECarryDQ3QQ'DClk00001syHASI3Q2QQ'DClk22201syHASI2Q1QQ'DClk11101syHASI1Q0QQ'DClk00001syHASI0LoadEDOperations0 X no change1 0 count up1 1 count downEDQiCiCi+1DiComment100000100101101001101110adder: Qi + Ci = Di, andCi+1 is the carry.1100001 1 0 1 1 1 0-1 = borrow 2-1 = 11110011 1 1 1 0 0 1-1 = 0 with no borrowHalf Adder Subtractor (HAS) truth tableSubtractor: Qi – Ci = Di, and Ci+1 is the borrow.Load E DOperations0 0 X no change0 1 0 count up0 1 1 count down1 X X load the inputSection 7.1 − Storage Components Page 4 of 87.4 BCD CounterSelector0"0000"1"1001"I0I1I2I3Q3Q2Q1Q0LoadDEUp/down counter"0" "0" "0" "0""0"I0I1I2I3Q3Q2Q1Q0LoadDEUp/down counterBCD up counter BCD up/down counter7.5 Asynchronous CounterA counter without using an adder or subtractor.Achieved by toggling each flip-flop at half the frequency of the preceding flip-flop.QQ'TClk033QQ'TClk022QQ'TClk011QQ'TClk000ClearClkEQ3Q2Q1Q0Clear Clear Clear Clear4-bit asynchronous up counterSection 7.1 − Storage Components Page 5 of 87.6 Register FilesQQ'DClk000ClkInputWriteSelectReadSelectOutputRFCRF2nxmWAWEClkImnRAREnOmRegister file cell Graphic symbolRFC RFC RFC RFCRFC RFC RFC RFCRFC RFC RFC RFCRFC RFC RFC RFC2-to-4readdecoder01232-to-4readdecoder0123WA1WA0WERA1RA0REI3I2I1I0O0O1O2O3Register file with one write port and one read portQQ'DClk000ClkInputWriteSelectRS_AOutARFCOutBRS_BRegister file cell with two read portsSection 7.1 − Storage Components Page 6 of 87.7 Random-Access Memory (RAM)QQ'D0InputRowselectWriteenableOutputCMCRAM2nxmWriteCSAn-1A0A1I/Om-1O1O0Memory cell Graphic symbol2-to-4readdecoder0123A1A0IO0IO1IO2IO3MCMCMCMCMCMCMCMCMCMCMCMCMCMCMCMCCSWriteWriteenableReadenableRAMSection 7.1 − Storage Components Page 7 of 8To obtain wider bit widths, we can connect several memory chips in parallel.8 8 8 832Input bus14ACSWriteM3D0 - D7A0 - A13CSWrite16K x 8M3D0 - D7A0 - A13CSWrite16K x 8M3D0 - D7A0 - A13CSWrite16K x 8M3D0 - D7A0 - A13CSWrite16K x 8214 = 16384 = 16K = 0000 to 3FFF16K x 32 RAM obtained by connecting in parallel four 16K x 8 RAMs.Section 7.1 − Storage Components Page 8 of 8To obtain a larger memory, we can connect several memory chips in series.2-to-4 decoder0123A WriteDatabus141228M0D0-D7A0-A11CSWrite4K x 8M1D0-D7A0-A11CSWrite4K x 8M2D0-D7A0-A11CSWrite4K x 8M3D0-D7A0-A11CSWrite4K x 8A12-A130000 - 0FFF1000 - 1FFF2000 - 2FFF3000 - 3FFF16K x 8 RAM obtained by connecting in series four 4K x 8 RAMs.212 = 4096 = 4K = 000 to FFFA0– A11 Address Bytes0 0 000 –FFF 4096214 = 16384 = 16K = 0000 to 3FFFA12 – A13 Address Bytes0 0 0000 –0FFF 40960 1 1000 – 1FFF 81921 0 2000 – 2FFF 122881 1 3000 – 3FFF