Section 6.1 − Sequential Logic – Flip-Flops Page 1 of 56. Sequential Logic – Flip-FlopsCombinatorial components: their output values are computed entirely from their present input values.Sequential components: their output values are computed using both the present and past input values.In other words, their outputs depend on the sequence of input values that have occurred over a period of time.This dependence on the past input values requires the presence of memory elements.The values stored in memory elements define the state of a sequential component.Since memory is finite, therefore, the sequence size must always be finite, which means that the sequential logiccan contain only a finite number of states.So sequential circuits are sometimes called finite-state machines.Sequential circuits can be a asynchronous or synchronous.Asynchronous sequential circuits change their state and output values whenever a change in input values occurs.Synchronous sequential circuits change their states and output values at fixed points of time, which are specifiedby the rising or falling edge of a free-running clock signal.Clock period is the time between successive transitions in thesame direction, i.e., between two rising or two falling edges.Clock frequency = 1/clock periodClock width is the time during which the value of the clock signalis equal to 1.Duty cycle is the ratio of clock width and clock period.Active high if the state changes occur at the clock's rising edge orduring the clock width.Active low if the state changes occur at the clock's falling edge.Latches and flip flops are the basic storage elements that can store one bit of information.6.1 SR LatchThe simplest memory element.Consists of two cross-coupled NOR gates.Inputs S (set) and R (reset) are normally 0.Both active high.Asserting S (setting S=1) will make output Q=1.Asserting R (setting R=1) will make Q=0.t1t0 t2 t3 t4 t5 t6 t7 t8 t9 t101.4 1.4 1.4 1.41.41.41.41.42.82.82.8SRQQ'One problem inherent in the SR latch is the fact that if both S and R are disasserted at the same time, we cannotpredict the latch output (as in t10).The SR latch can also be implemented with NAND gates.S and R are normally 1. They are active low.Clock width Rising edge Falling edgeClock periodQ'QSR1001QQ'SRSRQQnextQ'next0000 10011 001x0 110x1 011x0 0nand 0 1011110nor 0 1010100SRQQnextQ'next00x1 001x1 010x0 11100 11111 0Section 6.1 − Sequential Logic – Flip-Flops Page 2 of 56.2SR Latch with EnableSimilar to the SR latch but with the extra controlinput C which enables or disables the operationof the S and R inputs.When C=1, the gated SR latch operates as an SRlatch.When C=0, S and R are disabled and the circuitpersists in the preceding state.6.3 Gated D LatchD latch ensures that inputs S and R never equal to 1 at the same time.Also SR latches are useful in control applications where we often think in terms of setting or resetting a flag to somecondition.However, we often need latches to store bits of information and a D latch may be used in such an application.Gated D latch is constructed from a gated SR latch with an inverter added between the S and the R inputs and use asingle D (data) input.The C (control) input is active high in this design but can also be active low.When the C input is asserted, the Q output follows the D input. In this situation, the latch is said to be “open” andthe path from D input to Q output is “transparent”; the circuit is often called a transparent latch for this reason.When the C input is negated, the latch “closes”; the Q output retains its last value and no longer changes in responseto D.Latches are often called level-sensitive latches because they are enabled and transparent whenever C is asserted.Method 2: Gated D latch can also be implemented using a multiplexer.negative latchD passes to Q when C=001syDQclkpositive latchD passes to Q when C=101syDQclk4.0 2.0CDQ4.03.0tsetuptholdDelay through one AOI gates is 2.0Problem with the D latch: there is a (shaded) window of time around the falling edge of C when the D input must notchange. This window begins at time tsetup before the falling (latching) edge of C; tsetup is called the setup time.The window ends at time thold afterward; thold is called the hold time.22Q'QSRC22QQ'DC1110QQ'DCCSRQQnext0xx000xx111000010011101x0110x1111xNACDQQnext0x000x1110x011x1nor 0 1010100Section 6.1 − Sequential Logic – Flip-Flops Page 3 of 56.4 D Flip-FlopA positive-edge-triggered D flip-flop combines a pair of D latches1.It samples its D input and changes its Q and Q’ outputs only at therising edge of a controlling CLK signal.When CLK=0, the first latch, called the master, is enabled (open) andthe content of D is transferred to QM.When CLK=1, the master latch is disabled (closed) and its output istransferred to the second latch, called the slave.The slave latch is open all the while that CLK=1, but changes only atthe beginning of this interval, because the master is closed andunchanging during the rest of the interval.Advantage: since the master and slave latches are never enabled at thesame time, the entire master-slave flip-flop is never transparent.4.03.0CLKDQM4.0Q3.05.0 4.04.0Like a D latch, the edge-triggered D ff has a setup and hold time window during which the D inputs must notchange. This window occurs around the triggering edge of CLK (rising clock edge for a positive-edge-triggeredff and falling clock edge for a negative-edge-triggered ff).If the setup and hold times are not met, the ff output will usually go to a stable, though unpredictable, 0 or 1 state. Insome cases, however, the output will oscillate or go to a metastable state halfway between 0 and 1.All propagation delays are measured from the triggering edge of CLK, since that’s the only event that causes anoutput change.A negative-edge-triggered D flip-flop simply inverts the clock input, so that all the action takes place on the fallingedge of the clock.There are many different ways to construct flip-flops, but they all exhibit the following two characteristics:• a ff will change state only on the positive or negative edge of the clock signal.• its data inputs must not change after time tsetup and before thold.All ffs can be divided into four basic types: SR, JK, D, and T. 1 (Gajski differentiates between master-slave ff and edge-triggered ff. Wakerly and many other books say the edge-triggered ff is the master-slave ff.)QQ'DCQMQDCCLKDQQ'master latch slave latchDCLK Q