1University of Florida, EEL 4744 – File #05© Drs. Schwartz & ArroyoAssembly,Addr Modes,Instructions,BUFFALO31-Aug-01—10:03 AMEEL 47441University of Florida, EEL 4744 –File #05© Drs. Schwartz & ArroyoEEL 4744Menu• Programming Model for the MC68HC11 µP System• Assembly Programming• Addressing Modes for 68HC11• Instruction set• BUFFALO (Bit User’s Fast Friendly Aid to Logical Operation) Monitor Program• Interrupt Vector Jump tableLook into my ...See examples on web-site: ImmAddr.asm, DirAddr.asm, ExtAddr.asm,IndAddr.asm, BUF34-as.asm, BUF34-as.lstEEL 47442University of Florida, EEL 4744 –File #05© Drs. Schwartz & ArroyoEEL 4744Programming Model for Motorola 68HC11TD: Fig.3-1. Programming Model7 I.R. 0STACKCCRACCBACCAIXHIXLIYHIYLPCHPCLSP-9SP-8SP-7SP-6SP-5SP-4SP-3SP-2SP-1SPSP BEFOREINTERRUPTSP AFTERINTERRUPT07 07A BD 015015015015015IXIYSPPC8-BIT ACCUMULATORS A AND BOR16-BIT DOUBLE ACCUMULATOR DINDEX REGISTER XINDEX REGISTER YSTACK POINTERPROGRAM COUNTER07CONDITION CODE REGISTER (CCR)CARRY/BORROW FROM MSBOVERFLOWZERONEGATIVEINTERRUPT MASKHALF CARRY (FROM BIT 3)X INTERRUPT MASKSTOP DISABLES X H I N Z V COur 68HC11 (68HC11-E9) has:512 bytes of RAM:$0000-$00FF and $0100-$01FF512 bytes of EEPROM:$B600-$B7FF12K of ROM: (Buffalo Monitor)$D000-$FFFFInternal Registers:$1000-$103F2University of Florida, EEL 4744 – File #05© Drs. Schwartz & ArroyoAssembly,Addr Modes,Instructions,BUFFALO31-Aug-01—10:03 AMEEL 47443University of Florida, EEL 4744 –File #05© Drs. Schwartz & ArroyoEEL 4744General-Purpose Registersv Within the 68HC11 MCU, there are two general-purpose registers. They are referred to as 8-bit registers A and B or alternatively as a 16-bit register D. v Registers A and B, often called accumulators, are the most important data registers in the 68HC11. A and B can store 8-bit numbers. [Examples]LDAA VALUE1 ; Move the byte at location VALUE1 to Register A.LDAB VALUE2 ; Move the byte at location VALUE2 to Register B.ABA ; Add the byte in Register B to A, the sum replaces ; the content of Register A.ROLA ; Rotate the contents of Register A to the left by 1 bit.EEL 47444University of Florida, EEL 4744 –File #05© Drs. Schwartz & ArroyoEEL 4744General-Purpose Registersv Registers A and B are sometimes treated together as a single 16-bit register D in some instructions.[Examples] LDD WORD1 ; The 16-bit word at location WORD1 is moved to Register D.* (A number is stored in A and B treated as 16-bit register D).ADDD WORD2 ; The 16-bit word at location WORD2 is added to Register D.v Most (but not all) of the instructions that involve an 8-bit register can use either A or B as one of the instruction operands. The instruction set of the 68HC11 is said to be nearly symmetric. Symmetric instruction sets are programmer friendly in that the programmer need only remember a single instruction mnemonic.[Examples] LDA (LDAA and LDAB), STA (STAA and STAB),ROL (ROLA and ROLB), etc.3University of Florida, EEL 4744 – File #05© Drs. Schwartz & ArroyoAssembly,Addr Modes,Instructions,BUFFALO31-Aug-01—10:03 AMEEL 47445University of Florida, EEL 4744 –File #05© Drs. Schwartz & ArroyoEEL 4744Special-Purpose Registers: CCR & IX/IYv Index Registers (IX and IY): The 16-bit registers used to store the index value for operands retrieved using the indexed addressing mode.v Condition Code Register (CCR): An 8-bit flag register in which condition codes (binary flags) are stored and tested.CONDITION CODE REGISTERS - Stop DisableX - X Interrupt MaskH - Half CarryI - I Interrupt MaskN - NegativeZ - ZeroV - Arithmetic OverflowC - Carry/BorrowS X H I N Z V CEEL 47446University of Florida, EEL 4744 –File #05© Drs. Schwartz & ArroyoEEL 4744Flags in CCRThere are five condition flags associated with the execution of the arithmetic instructions of the M68HC11. Half-Carry Flag (H): Set (to 1) if a carry occurs between bits 3 and 4 during ADD, ABA, or ADC instructions; otherwise, it is reset (to 0).Negative Flag (N): Set if the result of the last arithmetic, logic, or data manipulation operation was negative; otherwise, it is reset.Zero (Z): Set if the result of the last arithmetic, logic, or data manipulation operation was zero; otherwise, it is reset.Overflow (V): Set if the last operation caused an arithmetic overflow; otherwise, it is reset. Ex: Set if the addition of two positive #’s (negative #’s) result in an apparently negative # (positive #). Carry (C): If an instruction operation results in a carry (from addition) or a borrow (from subtraction or comparison) out of bit 7 of theresulting value, then the Carry flag is set; otherwise, it is reset.4University of Florida, EEL 4744 – File #05© Drs. Schwartz & ArroyoAssembly,Addr Modes,Instructions,BUFFALO31-Aug-01—10:03 AMEEL 47447University of Florida, EEL 4744 –File #05© Drs. Schwartz & ArroyoEEL 4744Special-Purpose Registers:PC & SPv Program Counter (PC): A 16-bit register whose content addresses the memory location that contains the next instruction to be executed.v Stack Pointer (SP): A 16-bit register which contains the address of the memory location in which the top of the stack is stored.Note: Stack vs. QueueLIFO FIFOStackQueueEEL 47448University of Florida, EEL 4744 –File #05© Drs. Schwartz & ArroyoEEL 4744v Programming a microprocessor in an assembly language is somewhatlike using an OLD electronic calculator. To use a calculator we must know what operations the calculator can perform. v For a µP system, the set of allowed operations, called an instruction set, is a great deal more extensive than that of non-programmable calculators, and includes operations such as LOAD, SHIFT, STORE, and JUMP, in addition to ADD, SUBTRACT, MULTIPLY, DIVIDE, and so on.v Further, the register structure of a µP system is a great deal more extensive, having different types of internal registers and external registers, as well as memory registers. To make full use of a µP system, we must know its register structure and fully understand its instruction set.Assembly Language Programming5University of Florida, EEL 4744 – File #05© Drs. Schwartz & ArroyoAssembly,Addr Modes,Instructions,BUFFALO31-Aug-01—10:03 AMEEL 47449University of Florida, EEL 4744 –File #05© Drs. Schwartz & ArroyoEEL 4744v For the microprocessor to understand our commands, each instruction must conform to a specific format. < The general format for an executable 68HC11 instruction >[Label:] Operation-Mnemonic