University of Florida EEL 4744 - Spring 2007 Dr. Eric M. Schwartz Electrical & Computer Engineering Dept. 6-Feb-07 Page 1/6 Revision 5 Lab 3: Memory and I/O Port Expansions OBJECTIVES • Explore and understand the implementation of memory-mapped I/O. Add an 8-bit input port and an 8-bit output port. • Add an 8kx8-bit block of useable SRAM (memory) using a 32kx8 (32KB) SRAM. REQUIRED MATERIALS 1 - 74HC573 8-bit 3-state transparent latch chip 1 - 74HC574 8-bit 3-state D flip-flop chip 1 - 32k x 8 (32KB) SRAM Chip (28-pin) 2 – 20-pin sockets (for ‘573 and ‘574) 1 – 28-pin socket (for SRAM) 3 - 0.1 µF bypass capacitors for 3 ICs From a previous lab: • 1 - 8-bit LED DIP Bank • 1 - 8-bit switch bank • 1 - DIP Rpack ~ 100 Ohms • 1 - SIP Rpack ~ 2.7 kOhms PRELAB REQUIREMENTS SUMMARY 1. Read the ENTIRE lab handout. 2. Provide assembly language (asm) and error-free list (lst) files as stated in this lab document. The file names are of the form: lab3_part#_section#_initials.asm. 3. Provide Quartus schematic (bdf) files or VHDL files as described in this lab document. 4. Modify the Quartus files above (or provide other files) to create a wiring schematic (with pin numbers shown) for the designs described in this lab document. PART 1 – INPUT/OUTPUT PORTS The 68HC12 has several input/output (I/O) ports. Each of the I/O pins on each port has additional non-I/O features we would like to use later in the semester. Therefore, we can “free up” these ports for their special use by adding other memory-mapped I/O ports as needed. 1. Generate the necessary chip-enable equations to implement one 8-bit input port and one 8-bit output port, both mapped to address $2000 and mirrored at all addresses from $2001 to $2FFF. Use partial-address decoding (also known as reduced-address decoding). Tri-state buffers must be used for input ports and flip-flops should be used for output ports. You will need to install the A12 jumper on J5 (under the A13 jumper that you already installed). 2. Use Quartus to add to the existing circuit diagram (or VHDL) that you made for your EEPROM (or EPROM) output-enable. [Figure 1 shows the schematics needed for the previous lab. You will add to this figure for this lab (and the next several labs). You could also accomplish this same design with VHDL.] Add both the input and the output Figure 1: EEPROM Output Enable and Complement of E YOU WILL NOT BE ALLOWED INTO YOUR LAB SECTION WITHOUT THE PRE-LAB AND YOUR FILES!!!!!University of Florida EEL 4744 - Spring 2007 Dr. Eric M. Schwartz Electrical & Computer Engineering Dept. 6-Feb-07 Page 2/6 Revision 5 Lab 3: Memory and I/O Port Expansions port chip-enable equations to this previous design. You will have to assign the extra input and output port chip-enables to two external CPLD pins. Refer to the UF 68HC12 board manual for CPLD/header pinouts. Section 6 contains a reference table. 3. Program your CPLD with the new schematic or VHDL design and verify that your board still boots, i.e., that the monitor’s welcome screen appears after hitting the reset button. If it doesn’t boot, review your chip-enable equations and pin assignments. INPUT PORT 4. Once the board boots, use the 74HC573 datasheet to create a wiring schematic (by hand or, preferably, with Quartus) for the input port using the 74HC573 8-bit 3-state transparent latch (acting as an 8-bit 3-state device). Use labels instead of wires to show connections. (I encourage you to make a computer-generated schematic that you can add to in subsequent labs.) The schematic should show connections to the data bus header (J30) and the CPLD header (J16). Do not draw wires. Use pin labels instead. Include all pin numbers. You can add the pin numbers by hand on your printouts. (Note: The 74573 is not available in Quartus, but the operation of the 74373 is identical and can be used. The 74373 can be found in the parts library under others | maxplus2. The pinouts of the ‘373 and the ‘573 are different.) 5. Wire the input port using your wiring schematic. Begin by first placing a socket on your board. Solder two corner pins to hold it in place. Then, solder a 0.1µF bypass capacitor between the corresponding 74HC573’s Vcc and GND pins, i.e., pins 10 and 20. Solder two low gauge wires (thicker than wire wrap wires) to give the chip power and ground. Wires from your 3701 kits can be used. Finally, wire-wrap all the signals as shown on your circuit diagram. Note: Power and Ground signals are usually distributed using a bus for each to every chip. Wire-wrap is usually too thin and therefore provides too much resistance. In our case, two wire-wrap wires are probably sufficient, but are not allowed in this course. In this course and in future projects (senior design for example) you should solder power bus lines as shown in the soldering video. 6. Once the input port is finished, verify that your board still boots. If the monitor greeting does not come up, there may be a crossed or loose connection. Verify all of your connections using a digital multimeter. 7. Now that the board boots with the newly wired input port, remove the wire wrap from the switch bank from a previous lab (or add another switch bank circuit) and wire-wrap it to your new input port. 8. Verify that your board still boots. If the board does not boot, check the switch bank connections using a digital multimeter. 9. Test the input port with your switches using the monitor memory display (md) command. Memory locations $2000-$2FFF should show the same value as that of the switches. Try different test patterns. 10. If the input port does not work, you will have to review steps 4-8. Use a digital multimeter to verify that the voltages are correct throughout your input port components.University of Florida EEL 4744 - Spring 2007 Dr. Eric M. Schwartz Electrical & Computer Engineering Dept. 6-Feb-07 Page 3/6 Revision 5 Lab 3: Memory and I/O Port Expansions OUTPUT PORT 11. Once the input port works, use the 74HC574 datasheet to create a Quartus design for the output port using the 74HC574 8-bit 3-state D flip-flop. Also create a wiring schematic. Add your circuit diagram to the one with the input port and EEPROM. (As the semester continues, we will add to this schematic many times.) The schematic should show connections to the data bus header (J30) and the CPLD header (J16). Do not draw wires. Use pin