ECEN4827/5827 lecture notes Inside a simple two-stage CMOS op-amp: transistor-level view (part 1) Objectives in this segment of the course are: 1. Start to analyze the two-stage CMOS op-amp topology at the transistor level with the basic building blocks studied in prerequisite classes, including single-stage amplifiers, differential pairs, and current mirrors. 2. Review/recall some background materials in CMOS technology, device large- signal equations and operating regions when necessary in lectures. (NOT a repeat of ECEN3225; students who need to refresh this materials should go ahead and study the textbook references and lecture notes suggested or posted on the course website) Inside a two-stage CMOS op-amp Fig 6.2: Outside view of two-stage CMOS op-ampFig 6.3: Inside view of the two-stage CMOS op-amp Fig 6.2 and Fig 6.3 can be related to each other, note that the two inputs V(+) and V(-) of the op-amp are the gates of the transistors M2 and M1, respectively. How do we approach analysis of complex circuits at the transistor level? The general idea is to visualize the circuit as a combination of known, simpler functional blocks, and perform the analysis on these simpler functional blocks one by one, if possible. Identifying functional blocks in the two-stage op-amp circuit 1) We first note that the resistor R is the only passive element in this two-stage op-amp circuit: the function of R is biasing, i.e. setting up a constant dc bias current Ib. This current is then is replicated at various other locations for biasing other amplifier stages through current mirrors. In the op-amp circuit of Fig.6.3, the bias current Ib is the input current for the current mirror with two outputs: M5 and M7. 2) M8, M5, M7 combined together form current mirrors, distributing Ib to the rest circuit. Here, the input side of the mirror is M8. M5 and M7 are the two outputs of the mirror. Since M8, M5, M7 are sharing the same gate-source voltage, the driver source M8 can replicate the bias current Ib as needed for biasing throughout the rest of the circuit. Different aspect ratios W/L of the mirror output transistors with respect to the input transistor can be used to scale the bias currents as needed (more about this in the quantitative analysis later)3) M1 and M2 form the input differential pair, which is also the input of the first gain stage. I B1 is the biasing current for the differential pair M1 and M2. This bias current is provided by M5, which acts as a DC current source. 4) M3 and M4 form a current mirror that acts as the active load for M1 and M2. 5) M6 is the common source gain stage and it is also the second gain stage, note that the input of this gain stage is at node 1 which is the gate of M6, the output of this stage is at node 2 which is the drain of M6 and M6 is biased from node 1. The source of M6 is directly connected to the DC supply voltage VDD and hence no signal component. 6) M7 is the active load for M6. Comments: • In general, in IC design very few passive components are used, since they usually occupy significant area and have wide tolerances. Transistors are used instead, whenever possible. • In particular, note that (1) transistor current mirrors are used to replicate and distribute DC bias currents as needed and (2) active transistor loads are used instead of passive, resistive loads Analysis of the DC bias operating point of the two-stage CMOS op-amp Assumption: We’re placing the op-amp in a negative feedback circuit to make VO zero, away from saturation, as shown in the circuit below: Fig 6.4: (left) Open-loop opamp with both inputs tied to zero. (right) Closed-loop op-amp with negative feedback, VO = V(−) = 0. Here is the point: if we leave the op-amp open as in the circuit on the left, even a relatively small offset voltage VOS would easily drive the op-amp into saturation region, i.e., to one of the output voltage saturation limits. In a negative feedback circuit (right), the DC operating point is VO = V(−) ≈ 0, away from saturation. The DC analysis will beperformed under the assumption that the op-amp is placed in a negative-feedback circuit (such as the circuit on the right of Fig.6.4), so that the DC operating point is away from saturation limits. Solving for DC biasing We start by solving the DC bias current Ib through R. Starting from this simple circuit, we can calculate all other DC voltages and currents (i.e. the DC operating point) for other circuit blocks. Small signal calculations of the gain can then be performed after we solve for the DC operating point. Fig 6.5: DC biasing circuit DC solution in the above circuit is as follows: VDD – RIb - VGS8= -VSS (1) ID8 = Ib = (µnCox/2) * (W/L)8 (VGS8 – Vth )2 (2) Comments: • We can consider the circuit in Fig. 6.5 separately from the rest of the circuit because the only connection between this biasing circuit and the rest of the op-amp is through the gates of M8, M5, M7. Since the DC gate current of MOS transistors is essentially 0 (because of the oxide isolation layer between the gate and the channel, source or drain), the biasing circuit in Fig. 6.5 is not affected by other circuit blocks at all. • Equation (1) is simply the voltage-loop equations for the circuit in Fig.6.5. • Equation (2) is the characteristic of M8 in the active/saturation region. We know that M8 is in this operating region because the gate is shorted to drain, VGD = 0, which is less than the threshold voltage Vtn of the NMOS device.• Equations (1) and (2) can be solved for Ib, if the device parameters and R are given. In most cases, the desired value of the bias current Ib would be given, and (1) and (2) would be solved for