Random Offset in CMOS IC DesignECEN4827/5827 Analog IC DesignOctober 19, 2007Art Zirger, National [email protected] to start?• How do we choose what transistor sizes to use in a design?• One topic not often discussed in classes is random offsetand how transistor sizing affects this phenomenon.Introduction• 2 devices (MOSFET’s, resistors, capacitors) of the same size, laid out next to each other, are not identical.• How they differ is generally the function of random offsets during processing.• These offsets vary from chip to chip and set a limit on precision attainable which is typically reflected as data sheet specifications.Misc. Definitions/Notation• The following I-V equation for a MOSFET in saturation is used:where• A mixture of Vt& VTis used where both are referring to threshold voltage, not thermal voltage()22tGSDVVI −=βLWCoxµβ=AgendaSystematic vs. random offsetSources & profiles of random offsetCurrent Mirror/Diff Pair offset derivation & insightsPropagation of uncertainties mathCurrent Mirror/Diff Pair exercisesSystematic vs. random mismatch• Systematic– Mismatch in the circuit (or layout) because of poor designer choices (i.e. avoidable)– Each copy of the circuit should share this; calculable based on the average values of element parameters– Viewable using SPICE DC operating point simulation• Random– Mismatch in the circuit because of wafer processing– Different chips will have different values, but the value will mostly remain the same (subject to temperature shifts, drift, etc.)– Each copy of the circuit should share this; calculable based on the statistical values of element parameters– Viewable using DCmatch and Monte Carlo simulations– This is what is usually thought of as matchingSources of random mismatch• Sources of random mismatch include:– Edge effects (rough edges)– Implantation (finite number of charges & distribution)– Mobility– Oxide effectsSee References (after Summary slide) for more information.Mismatch parameters• Commonly investigated mismatch parameters:–MOSFETVt, β (mobility and W/L), γ (Body Effect)– Resistorsρ (resistivity)– Capacitorsoxide thickness variation• This presentation covers Vt& β mismatchProfile of random mismatch• Has a gaussian distribution• Can be quantified by statistical variables of:– mean: ā– standard deviation: σa– variance: σ2a– Mismatch is defined as occurring between elements; a single element does not have mismatch, but a “self mismatch” can be defined.Threshold Voltage MismatchThe threshold voltages among a group of transistors has a gaussian profile about a mean. Experimentally, it has been shown that the difference in threshold voltages between 2 identically sized transistors behaves as:Note that to reduce the mismatch by ½ takes 4 times the area…A fab will create test structures and measure ∆Vtmultiple times per wafer for various sizes of transistors and collect ongoing statistics to monitor the process over time.WLAttVV=∆σThreshold Voltage Mismatch, cont’dFrom W. Sansen showing how the mismatch constant, AVT, varies roughly linearly with process size (doping concentration affects linearity of the relationship). Also, for p substrates, the PMOS will have AVT~ 1.5*AVTNMOS.Our CMOS AVTNFETCurrent Factor MismatchCurrent Factor, β, behaves fractionally, as:Aβ~ 2%µm, invariant of processNational Semiconductor does not have this value characterized, so we may use this approximate value to estimate whether we need to worry about this or not.()WLAβββσ=∆Offset Derivation• Given the behavior of sufficiently uncorrelated parameters, want to know the effect of those parameters on 2 common circuits:– Current mirror– Differential pair• Start with I-V equation for MOSFET and apply “total differential”:...+∆∂∂+∆∂∂+∆∂∂=∆ zzfyyfxxffOffset Derivation – Current MirrorWhat is the fractional error in the currents being mirrored in a 1:1 current mirror?()22TgsDVVI −=βTgsVV ,,βvariablesDmIgβ2=TgsDVVI−2or()()()TgsgsTgsTTgsDVVVVVVVVI −∆+−∆−−∆=∆ 2222212βββ()()()()222222221TgsTgsTTgsTgsDDVVVVVVVVVII−−∆−−−∆=∆ββββ()TgsTDDVVVII−∆−∆=∆ 2ββ∆Vgs= 0 in a current mirror.Divide by IDto get fractional error:TDmDDVIgII∆−∆=∆ββOffset Derivation – Diff PairWhat is ∆VGSfor 2 transistors operating at the same current?()22TgsDVVI −=βTgsVV ,,βDmIgβ2=TgsDVVI−2or()()()TgsgsTgsTTgsDVVVVVVVVI −∆+−∆−−∆=∆ 2222212βββ0=∆DI()()gsTTgsTgsVVVVVV∆+∆−−−∆=222102ββConstant current so Divide by ()TgsVV −22β()TTgsgsVVVV ∆+−∆−=∆2ββTmDgsVgIV ∆+∆−=∆ββOffset Derivation – Summary/Insights• Differential Pairs and Current Mirrors operate with very different gm/Id(i.e. bias point) ratios to minimize mismatch errors:• Differential Pair:High gm/Id Æ low overdrive• Current Mirror:Low gm/Id Æ high overdrive• You can achieve this by designing differential pairs with large W/L and current mirrors with small W/LratiosTmDgsVgIV ∆+∆−=∆ββTDmDDVIgII∆−∆=∆ββOffset Derivation w/Standard Deviations• Given the expected functional relationships of the 2 different offset behaviors, for various statistical reasons, you express these relationships in terms of standard deviations as:Current Mirror Differential PairTDmDDVIgII∆−∆=∆ββTmDgsVgIV ∆+∆−=∆ββ()()()()22TmDgsVgIV ∆+∆=∆σββσσ() ()()22∆+∆=∆TDmDDVIgIIσββσσStatistics Math• You need to know how to propagate uncertainties to get the most out of this material.• General form to propagate uncertainties for uncorrelated variables:z = f(x,y,z…)( n = # of variables )∑=∂∂=nivizivf1222σσ...222+∂∂+∂∂=yxzyfxfσσσStatistics Math, cont’d• More commonly seen as this:•Sum: r.s.s, (square) root sum of squares• Product/Quotient: f(x,y) = x*y or x/yFractional error of f is the r.s.s of the fractional errors of the individualvariables.22yxzσσσ+=22+=yxfyxfσσσStatistics Math, cont’dTo utilize these error propagation formulas, you need to know the individual contributions (e.g. σx, σy) which means you need the