CSCE 230L Final Project Design of a Multi Cycle Processor Objectives 1 Understanding software hardware interface better by implementing a substantial subset of a RISC instruction set architecture ISA 2 Gain first hand knowledge about what determines theexperience with determinants of timing performance of in hardware designs 3 Learn to work as a team to carry out a complex design task requiring task partitioning effective communication and cooperation A Design Specification You are to design and implement on the UP2 board a multi cycle 16 bit processor that can carry out the instructions specified in Tables 1 and 2 The tables show the instruction subset to be implemented and examples of instruction encoding the meaning of most instructions remains the same as in MIPS Recall that in a multi cycle implementation instructions are executed in varying number of clock cycles You may refer to Chapter 5 for the concepts and many of the details involved in implementing the instruction set of a processor Sections 5 5 of the text focus on multi cycle implementation and Figure 5 28 shows the control and datapath of a multicycle MIPS microprocessor Table 1 Basic Instruction Set R type Instruction add 3 2 1 sub 3 2 1 and 3 2 1 or 3 2 1 xor 3 2 1 shft ll 2 1 set 2 1 jr 2 R Type Instruction OPCode RS 0000 0010 0001 0010 0010 0010 0011 0010 0100 0010 0101 0010 0110 0010 0111 0010 RT 0001 0001 0001 0001 0001 0001 0001 0000 RD 0011 0011 0011 0011 0011 1010 0000 0000 Table 2 Basic Instruction Set I type Instruction lwiu 1 20 lwil 1 20 40 b le 20 b v 20 lwx 1 20 X swx 1 20 X j 40 jal 40 optional I Type Instruction OPCode RS 1000 0001 10001 0001 1010 1100 1010 0010 1011 0001 1100 0001 1101 1110 Immediate 0001010000000000 00010100 00010100 00010100 00010100 00010100 000000101000 000000101000 The arithmetic and logical instructions are similar to MIPS Note that only 16 registers can be designated The shift instruction shft is a bit different The mode is designated by l left or r right c if c bit is seen appended on the left r if rotate instead of simple shift followed andby l logical or a arithmetic The contents of the first register is shifted by the amount in the second register The set instruction compares the contents of the two registers and records the result in a pair of flag bit registers associated with the ALU The resulting code is 10 for 01 for 11 for and 00 for The immediate instructions liu lwi and lil are is load word immediate upper and load immediate lower respectively immediate The next word in memory is loaded into the designated register The PC automatically jumps over the data word The lwi variant with 3 arguments is a PC relative load The programmer is responsible for avoiding executing the data Branching b is by a designated condition as determined by the four ALU flag bits The first two bits are those set referred to withby the set command The second two bits representing overflow v and carry out c are set by the add sub and shft commands Conditions include lt eq le and gt from the first two flag bits and v c and vc from the second two flag bits Load and store indexed lwx and swx are always relative to a specific index register designated as X This is actually register 1 We will use the RAM for memory The initial value size of RAM must be set to 256 x 16 bits Refer to Appendix A for memory initialization We may provide you several components including RAM Clock Generator 1 HZ Clock and 7 segment B Design The design flow consists of five steps 1 Block level Datapath Diagram 2 Design of Individual Components 3 Datapath Integration 4 Control Unit Design 5 System Integration Figure 5 28 of the text may be used to guide you through these design steps The major components described in the textbook can be adopted almost directly but the individual component design will need to be modified to accommodate the changes in the requirements You may assume that the memory 256x16 bit RAM is only addressable at 16 bit word boundaries This means that the program counter could be designed to increment by 1 instead of 2 Further we assume the data word length is 16 bits and only 16 bit wordlength operations are to be implemented by the ALU By taking the above considerations into account and by referring to Section 5 5 of the textbook you should be able to complete the datapath diagram and determine the components necessary for the datapath At this point a good strategy would be to partition the task of component level design among the team members As each component design is completed be sure to verify its functional correctness by comprehensive testing see the next section for more on design verification For this project the control unit will be a simulated PLA and a state register You can combine the sequencing control and the ALU Control into a single unit or design them separately as shown in Figure 5 28 After you have designed the datapath and the control unit and you have verified their functional correctness you will need to integrate the two parts and verify that the whole system processor works according to the specification C Verification Design verification is an integral and important part of any design process and this will be factored into judging the quality of your project Therefore you should consider how you would verify each component and their integration before you carry out their design It is sufficient for this project to consider design verification via carefully chosen test cases for simulation For example to verify the correctness of the processor design you could implement in software machine instructions the multiplication algorithm given in Figure 3 6 of the textbook for two 8 bit numbers Assume the two numbers are initially stored in the RAM Refer to the end of this file about Memory Initialization in Altera UP 2 board To implement the multiplication algorithm you should follow the steps as below 1 Load mutiplier from RAM 2 Load mutiplicand from RAM 3 Implement Multiplication Algorithm 4 Store Results to RAM The design is expected to display the values of registers in the register file on the two seven segment displays Since there are only two seven segments you would also need to specify whether you want to see the upper or lower half of the register You may use the DIP dual inline pins switch to select the register you would like to see As there are 8 binary switches in the DIP switch you can use four to select a register and another one to select the upper or the