Chapter 2 1 2004 Morgan Kaufmann Publishers Instructions Language of the Machine We ll be working with the MIPS instruction set architecture similar to other architectures developed since the 1980 s Almost 100 million MIPS processors manufactured in 2002 used by NEC Nintendo Cisco Silicon Graphics Sony 1400 900 Other SPARC Hitachi SH PowerPC Motorola 68K MIPS IA 32 800 ARM 1300 1200 1100 1000 700 600 500 400 300 200 100 0 1998 1999 2000 2001 2002 2 2004 Morgan Kaufmann Publishers MIPS arithmetic All instructions have 3 operands Operand order is fixed destination first Example C code a b c MIPS code add a b c we ll talk about registers in a bit The natural number of operands for an operation like addition is three requiring every instruction to have exactly three operands no more and no less conforms to the philosophy of keeping the hardware simple 3 2004 Morgan Kaufmann Publishers MIPS arithmetic Design Principle simplicity favors regularity Of course this complicates some things C code a b c d MIPS code add a b c add a a d Operands must be stored in registers only 32 registers are provided Each register contains 32 bits Design Principle smaller is faster Why 4 2004 Morgan Kaufmann Publishers Registers vs Memory Arithmetic instructions operands must be stored in registers only 32 registers provided Compiler associates variables with registers What about programs with lots of variables Control Input Memory Datapath Processor Output I O 5 2004 Morgan Kaufmann Publishers Memory Organization Viewed as a large single dimension array with an address A memory address is an index into the array Byte addressing means that the index points to a byte of memory 0 1 2 3 4 5 6 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 6 2004 Morgan Kaufmann Publishers Memory Organization Bytes are nice but most data items use larger words For MIPS a word is 32 bits or 4 bytes 0 32 bits of data 4 32 bits of data Registers hold 32 bits of data 8 32 bits of data 12 32 bits of data 232 bytes with byte addresses from 0 to 232 1 230 words with byte addresses 0 4 8 232 4 Words are aligned i e what are the least 2 significant bits of a word address 7 2004 Morgan Kaufmann Publishers Instructions Load and store instructions Example C code A 12 h A 8 MIPS code lw t0 32 s3 add t0 s2 t0 sw t0 48 s3 Can refer to registers by name e g s2 t2 instead of number Store word instruction has destination operand last Remember arithmetic operands are in registers not memory Can t write add 48 s3 s2 32 s3 8 2004 Morgan Kaufmann Publishers Our First Example Can we figure out the code swap int v int k int temp temp v k v k v k 1 v k 1 temp swap muli 2 5 4 add 2 4 2 lw 15 0 2 lw 16 4 2 sw 16 0 2 sw 15 4 2 jr 31 9 2004 Morgan Kaufmann Publishers So far we ve learned MIPS loading words but addressing bytes arithmetic on registers only Instruction Meaning add s1 s2 s3 sub s1 s2 s3 lw s1 100 s2 sw s1 100 s2 s1 s2 s3 s1 s2 s3 s1 Memory s2 100 Memory s2 100 s1 10 2004 Morgan Kaufmann Publishers Machine Language Instructions like registers and words of data are also 32 bits long Example add t1 s1 s2 registers have numbers t1 9 s1 17 s2 18 Instruction Format 000000 10001 10010 op rs rt 01001 00000 100000 rd shamt funct Can you guess what the field names stand for 11 2004 Morgan Kaufmann Publishers Machine Language Consider the load word and store word instructions What would the regularity principle have us do New principle Good design demands a compromise Introduce a new type of instruction format I type for data transfer instructions other format was R type for register Example lw t1 32 s2 35 18 9 op rs rt 32 16 bit number Where s the compromise 12 2004 Morgan Kaufmann Publishers Stored Program Concept Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data programs compilers editors etc Fetch Execute Cycle Instructions are fetched and put into a special register Bits in the register control the subsequent actions Fetch the next instruction and continue 13 2004 Morgan Kaufmann Publishers Control Decision making instructions alter the control flow i e change the next instruction to be executed MIPS conditional branch instructions bne t0 t1 Label beq t0 t1 Label Example if i j h i j bne s0 s1 Label add s3 s0 s1 Label 14 2004 Morgan Kaufmann Publishers Control MIPS unconditional branch instructions j label Example if i j h i j else h i j beq s4 s5 Lab1 add s3 s4 s5 j Lab2 Lab1 sub s3 s4 s5 Lab2 Can you build a simple for loop 15 2004 Morgan Kaufmann Publishers So far Instruction Meaning add s1 s2 s3 sub s1 s2 s3 lw s1 100 s2 sw s1 100 s2 bne s4 s5 L beq s4 s5 L j Label s1 s2 s3 s1 s2 s3 s1 Memory s2 100 Memory s2 100 s1 Next instr is at Label if s4 s5 Next instr is at Label if s4 s5 Next instr is at Label Formats R op rs rt rd I op rs rt 16 bit address J op shamt funct 26 bit address 16 2004 Morgan Kaufmann Publishers Control Flow We have beq bne what about Branch if less than New instruction if s1 s2 then t0 1 slt t0 s1 s2 else t0 0 Can use this instruction to build blt s1 s2 Label can now build general control structures Note that the assembler needs a register to do this there are policy of use conventions for registers 17 2004 Morgan Kaufmann Publishers Policy of Use Conventions Name Register number 0 zero 2 3 v0 v1 4 7 a0 a3 8 15 t0 t7 16 23 s0 s7 24 25 t8 t9 28 gp 29 sp 30 fp 31 ra Usage the constant value 0 values for results and expression evaluation arguments temporaries saved more temporaries global pointer stack pointer frame pointer return address Register 1 at reserved for assembler 26 27 for operating system 18 2004 Morgan Kaufmann Publishers Constants Small constants are used quite frequently 50 of operands e g A A 5 B B 1 C C 18 Solutions Why not put typical constants in memory and load them create hard wired registers like zero for constants like one MIPS Instructions addi 29 29 4 slti 8 18 10 andi 29 29 6 ori 29 29 4 Design Principle Make the common case fast Which format 19 2004 Morgan Kaufmann Publishers How about larger constants We d like to be able to load a 32 bit constant into a register …