1CSCI 8150Advanced Computer ArchitectureHwang, Chapter 4Processors and Memory Hierarchy4.1 Advanced Processor TechnologyDesign Space of ProcessorsProcessors can be “mapped” to a space that has clock rate and cycles per instruction (CPI) as coordinates. Each processor type occupies a region of this space.Newer technologies are enabling higher clock rates.Manufacturers are also trying to lower the number of cycles per instruction.Thus the “future processor space” is moving toward the lower right of the processor design space.CISC and RISC ProcessorsComplex Instruction Set Computing (CISC) processors like the Intel 80486, the Motorola 68040, the VAX/8600, and the IBM S/390 typically use microprogrammed control units, have lower clock rates, and higher CPI figures than…Reduced Instruction Set Computing (RISC) processors like the Intel i860, SPARC, MIPS R3000, and IBM RS/6000, which have hard-wired control units, higher clock rates, and lower CPI figures.Superscalar ProcessorsThis subclass of the RISC processors allow multiple instructoins to be issued simultaneously during each cycle.The effective CPI of a superscalar processor should be less than that of a generic scalar RISC processor.Clock rates of scalar RISC and superscalar RISC machines are similar.VLIW MachinesVery Long Instruction Word machines typically have many more functional units that superscalars (and thus the need for longer – 256 to 1024 bits –instructions to provide control for them).These machines mostly use microprogrammed control units with relatively slow clock rates because of the need to use ROM to hold the microcode.2Superpipelined ProcessorsThese processors typically use a multiphase clock (actually several clocks that are out of phase with each other, each phase perhaps controlling the issue of another instruction) running at a relatively high rate.The CPI in these machines tends to be relatively high (unless multiple instruction issue is used).Processors in vector supercomputers are mostly superpipelined and use multiple functional units for concurrent scalar and vector operations.Instruction PipelinesTypical instruction includes four phases:fetchdecodeexecutewrite-backThese four phases are frequently performed in a pipeline, or “assembly line” manner, as illustrated on the next slide (figure 4.2).Pipeline DefinitionsInstruction pipeline cycle – the time required for each phase to complete its operation (assuming equal delay in all phases)Instruction issue latency – the time (in cycles) required between the issuing of two adjacent instructionsInstruction issue rate – the number of instructions issued per cycle (the degree of a superscalar)Simple operation latency – the delay (after the previous instruction) associated with the completion of a simple operation (e.g. integer add) as compared with that of a complex operation (e.g. divide).Resource conflicts – when two or more instructions demand use of the same functional unit(s) at the same time.Pipelined ProcessorsA base scalar processor:issues one instruction per cyclehas a one-cycle latency for a simple operationhas a one-cycle latency between instruction issuescan be fully utilized if instructions can enter the pipeline at a rate on one per cycleFor a variety of reasons, instructions might not be able to be pipelines as agressively as in a base scalar processor. In these cases, we say the pipeline is underpipelined.CPI rating is 1 for an ideal pipeline. Underpipelined systems will have higher CPI ratings, lower clock rates, or both.Processors and CoprocessorsCentral processing unit (CPU) is essentially a scalar processor which may have many functional units (but usually at least one ALU – arithmetic and logic unit).Some systems may include one or more coprocessors which perform floating point or other specialized operations –INCLUDING I/O, regardless of what the textbook says.Coprocessors cannot be used without the appropriate CPU.Other terms for coprocessors include attached processorsor slave processors.Coprocessors can be more “powerful” than the host CPU.3Instruction Set ArchitecturesCISCMany different instructionsMany different operand data typesMany different operand addressing formatsRelatively small number of general purpose registersMany instructions directly match high-level language constructionsRISCMany fewer instructions than CISC (freeing chip space for more functional units!)Fixed instruction format (e.g. 32 bits) and simple operand addressingRelatively large number of registersSmall CPI (close to 1) and high clock ratesArchitectural DistinctionsCISCUnified cache for instructions and data (in most cases)Microprogrammed control units and ROM in earlier processors (hard-wired controls units now in some CISC systems)RISCSeparate instruction and data cachesHard-wired control unitsCISC Scalar ProcessorsEarly systems had only integer fixed point facilities.Modern machines have both fixed and floating point facilities, sometimes as parallel functional units.Many CISC scalar machines are underpipelined.Representative systems:VAX 8600Motorola MC68040Intel Pentium4RISC Scalar ProcessorsDesigned to issue one instruction per cycleRISC and CISC scalar processors should have same performance if clock rate and program lengths are equal.RISC moves less frequent operations into software, thus dedicating hardware resources to the most frequently used operations.Representative systems:Sun SPARCIntel i860Motorola M88100AMD 290005SPARCs and Register WindowsThe SPARC architecture makes clever use of the logical procedure concept.Each procedure usually has some input parameters, some local variables, and some arguments it uses to call still other procedures.The SPARC registers are arranged so that the registers addressed as “Outs” in one procedure become available as “Ins” in a called procedure, thus obviating the need to copy data between registers.This is similar to the concept of a “stack frame” in a higher-level language.CISC vs. RISCCISC AdvantagesSmaller program size (fewer instructions)Simpler control unit designSimpler compiler designRISC AdvantagesHas potential to be fasterMany more registersRISC ProblemsMore complicated register decoding systemHardwired control is less flexible than microcodeSuperscalar, Vector ProcessorsScalar processor: executes one instruction per cycle, with only one instruction pipeline.Superscalar processor: multiple instruction pipelines, with multiple instructions issued per