1Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 1Z. AliyaziciogluElectrical and Computer Engineering DepartmentCal Poly PomonaECE341-2. Sequential NetworkECE 341-04 Computer Engineering ICal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 2Register• Registers are formed from a collection of flip-flops, like counters.• Data storage is the main function of a registerxclockLoaddataxdataParallel Input/Output1clockdata1dataSerial Input/OutputxclockLoaddata1dataParallel Input/Serial Output1clockLoaddataxdataSerial Input/ Parallel Output2Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 31DClockclearD4 Bit RegisterCRDCRDCRDCR2D3D4D1Q2Q3Q4Q1Q2Q3Q4Q1DDCRDCR2DOutputDataD0-D3Parallel Input/Output Register44488ClockclearD4-D78 Bit Register using 2x4 bit registerCal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 4SCRQQSCRQQQQSCRQQSCRQQSCRQQSCRQQClockRight-shift Serial Input Output RegisterQ1Q2Q3Q4Q5Q60010000t40100000t50001000t30000100t20000010t10000001t0Q6Q5Q4Q3Q2Q1In3Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 5Counter• Asynchronous Up-Counter with T Flip FlipTCQQTQQTCQQQ11Clock CQ2Q0Q0Q0Q0Clock0 1 2 3 4 5 6 7 0Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 6Counter• Asynchronous Down-Counter with T Flip FlipTCQQTQQTCQQQ11Clock CQ2Q0Q0Q0Q0Clock0 7 6 5 4 3 2 1 04Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 7Counter• Synchronous 4-bit Up counter with T Flip-FlopTCQQTQQTCQQQ11Clock CQ2Q0TCQQQ3T0=1T1=Q0T2=Q0Q1T3=Q0Q1Q2…Tn=Q0Q1…Qn-1000811170116101500141103010210010000Q0Q1Q2ClockQ1changesQ2changesCal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 8Clocked Sequential Network• We will consider sequential networks which have clock pulse input and additional inputs. So that sequence of output flip-flop states will depend on the input sequence. • Two types of clocked sequential network will be considered.1. Moore machine• The output depends only on the present state of the flip-flop which is referred as a Moore machine. The outputs change synchronously with the state transition and the clock edge.CombinationalNetworkStateRegisterInputsCombinational NetworkOutputsClockFeedbackSEE=f(Input,St)St+1=f(E,St)Output=f(St)5Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 9Mealy machine• 2. Mealy machine• The output depends on the present state and the present value of the inputs which is referred as Mealy machine.• The output can change immediately after a change at the inputs, independent of the clock. Mealy machine has asynchronous output. CombinationalNetworkStateRegisterOutputsInputsClockFeedbackCom.NetworkE=f(Input,St)St+1=f(E,St)Output=f(G, St)SGECal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 10State Diagram• The symbolic notation for a one input, one output Mealy sequential circuit state diagramS1S2X’/Y’X’/YX/Y’X/Y’X : input VariableY : Output variableS1 and S1 are symbols representing different statesX/Y indicates input/outputIf input variable X=0, then the machine remains in state S1and Output is 0 If input variable X=1, then transition to state S2 and Output is 0The output is is a function of both the present state and the input6Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 11• In Moore machine, the output is dependent on only the present state. We represent the output inside of the state circle.• Here is an example of state graph for Moore circuit notations ofa J-K flip-flopS10S2100,0101,1110,1100,10Output variables written under state Variable namesIf S1 is present state, thenIf JK=00 and 01 machine remains state S1and output is 0If JK=10 and 11 transition to state S2and the output changes to 1If S2is present state, thenIf JK=00 and 10 machine remains state S2and output is 1If JK=01 and 11 transition to state S1and the output changes to 0Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 12Design a clocked Mealy sequential network• Network will examine a string of 0’s and 1’s applied to the X input and generate an output Z=1 only when a prescribed input sequence occurs.• The input X can only change between clock pulses. • We will design a network so that any input sequence ending in 101 will produce an output Z=1 coincident with the last 1. The network does not reset when a 1 output occurs.• A Typical input and corresponding output sequences010100000100000Z=010101001101100X=7Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 13• Let’s start with two state S0,S1, Later we will assign FF states to corresponding to the network states. • Initially we start the network in a reset state. If the input X=0 is received , the network can stay in S0. If X=1 is received, it will go to next state The label on the graph shows X/Z which X is input and Z is corresponding output.S0S11/00/0S0S11/00/0S20/01/11/00/0Mealy State Graph for Sequence Net.Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 14• Converting the state graph to a state table0 00 00 1S0 S1S2 S1S0 S1S0S1S2Present OutputX=0 X=1Next StateX=0 X=1Present State• We have three states, so we need two FF since one FF has two states. Let FF states A=0, B=0 correspond to network state S0, A=0,B=1 correspond to networks state S1. A=1,B=0 correspond to networks state S2. 0 00 00 100 0110 0100 01000110ZX=0 X=1Next State A+B+X=0 X=1Present StateAB8Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 150x000x10XAB00 01 11 1001A+=X’B1x110x00XAB00 01 11 1001B+=X1x000x00XAB00 01 11 1001Z=XACal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 16• Let’s use D F-F. DA=A+=X’B and DB=B+=XA’ ACKDB’ BCKDZX9Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 17Design a clocked Moore sequential network• Moore machine is similar to Mealy machine except that the output is written with the state instead of with the transition between states.• We will do the same problem with moore machine.• In Moore machine the output will be associated with states S0, S1, and S210S00S10S20010S00S10S200S3101101Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-2 18• Converting the state graph to a state table0 001S0 S1S2 S1S0 S3S2 S1S0S1S2S3Present OutputZNext StateX=0 X=1Present State• We