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Cal Poly Pomona ECE 341 - Introduction

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1Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 1ECE 341-02 Computer Engineering IECE341-1. IntroductionZ. AliyaziciogluElectrical and Computer Engineering DepartmentCal Poly PomonaCal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 2Instructors• Dr. Zekeriya Aliyazicioglu (Dr. Zeki)– Office: 9-143– http://www.csupomona.edu/~zaliyazici/ece341– [email protected]– 869-3667• Office Hours– M 12:00 PM - 2:00 PM, – W 12:00 PM - 2:00 PM, – TH 3:00 PM - 4:00 PM2Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 3Course Description• Analysis and design of Digital Systems using hardware (algorithmic state machines), and software (microcontrollers). • Four (4) one-hour lecture/problem solving sessions. • Prerequisites: ECE204/ 244, ECE220/270. • Concurrent: ECE 341L.• Note: Students are responsible for satisfying the required prerequisites.Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 4Course Objectives• To teach students how to design algorithmic state machines• To teach students how to use Verilog to describe and simulate digital systems• To teach students the architecture, instruction set, and programming of the Motorola 68HC11microcontroller• To teach student important applications of amicrocontroller.3Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 5Text Book• MC68HC11: An Introduction, Software and Hardware Interfacing, Huang, 2ndedition, ISBN 07668-1600-1• Further Reading(s):• Miller Gene H. Microcomputer Engineering, Prentice Hall, 2ndEdition, 1999.• [2[ Motorola MC68HC11 Reference Manual, Motorola University SupportCal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 6Grading• Homework, Quizzes, and Project effect the 25% of the final course grade• Exam 1 effects the 25% of the final course grade, • Exam 2 effects the 25% of the final course grade,• Final Exam effects the 25% of the final course grade• Note : Students are responsible for all materials/announcements presented in class whether they are present or absent.4Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 7Course Policies• Students must have the pre/co requisites for ECE 341 as given above.• No make-up tests will be given.• Students are encouraged to discuss the course, including issues raised by the assignments. However, the solutions to assignments should be individual original work unless otherwise specified. You may ask a fellow student a question designed to improve your understanding, not one designed to get the assignment done. To do otherwise is to cheat yourself out of understanding, as well as to be dishonorable. • Any case of cheating will result in an F grade for the course. Also, the case may be forwarded to the Department Chair for appropriate disciplinary action.Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 8Homework• Homework must be turned in at the beginning of your class• All work that you submit must represent your individualeffort• All assignments are expected to be prepared in a professional manner. • No late homework assignments will be accepted Computer failure or lack of availability of a computer are not valid excuses for late assignments5Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 9Questions• Questions before we begin?Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 10Latch• Latch : The memory element outputs immediately change in response to input change.• Example : R-S latch.• If a latch has only data input, like R and S , it is called unlocked latch. • Level-sensitive latches have an additional enable input, sometimes called the clock or control input.• Level-sensitive latches continuously sample their input while they are enabled.6Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 11Latch Q'QR S U2A 74LS02 5 6 4 U1A 74LS02 2 3 1 U1A74LS02231E'Q'QS'U4A74LS02231U3A74LS02231R'U2A74LS02231•Unlocked R-S latch. Level-sensitive R-S latchesSRQQ001101011010Last Q’Last Q00Q’QRSFunction TableSymbols for S-R latchundefinedCal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 12Flip-Flop• Flip-Flops are different than latches• Their outputs change only with respect to the clock.• We can characterize flip-flops on the the basic of the clock transition that causes the output change. There are positive edge-triggered, negative edge-triggered, flip-flops•A positive edge-triggered flip-flop samples its output on the low-to-high clock transition. The output change a propagation delay after rising clock transition•A negative edge-triggered flip-flop samples its output on the high-to-low clock transition7Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 13D- Flip-FlopClockDQClockLevel-sensitivelatch74LS76Positive edge-triggeredflip flopTTL 74LS74DClockNegative edge-triggeredflip flopQ’QQ’DQQ’CCKCKCal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 14D- Flip-FlopTiming behavior of s positive-edge-triggered D Flip-flopLast Q’Last Q11Last O’Last Q0001Ï110Ï0Q’QClkD8Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 15The Trigger Flip-Flop (T Flip-Flop)TQ’ QFFRFFSQ’ QR=QTS=Q’T01100 0 0 11 01 1Q+T QQ+=T’Q+TQ’=T⊕Q01100 0 0 11 01 1TQ Q+T= Q+⊕QTQCal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 16The Clocked Flip-FlopTQ’ QFFCKClockTQ01100 0 0 11 01 1Q+T QClock input has small circle indicates that the flip-flop changes state on the falling edge of the clock9Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 17The J-K Flip-FlopRFFSQ’ QKJConstruction from S-R FF01001110010101010011001100001111Q+QKJJQ’ QFFKCKQ+=QK’+Q’J0 X1 XX 1X 00 0 0 11 01 1J KQ Q+Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 18The Clocked J-K Flip FlopJQ’ QFFClockCKClockJKClock input has small circle indicates that the flip-flop changes state on the falling edge of the clockKQ10Cal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 19The D Flip-FlopDClockQQ’CK00110 0 0 11 01 1Q+D QQ+=DDQCal Poly Pomona Electrical & Computer Engineering Dept.ECE 341-1 20Clocked FF with Clear and PresetJClockQQ’CKKPRECLRPresetClearJ-K FF has Clear (CLR) and Preset (PRE) inputs. The small circle indicates that a logic 0 is


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