Outline for TodayMemory System Power ConsumptionOpportunity: Power Aware DRAMRDRAM as a Memory HierarchyRAMBUS RDRAM Main Memory DesignConventional Main Memory DesignExploiting the OpportunityPower-Aware DRAM Main Memory DesignPower-Aware Virtual Memory Based On Context SwitchesBasic IdeaSlide 12Rambus RDRAMRDRAM Active ComponentsDetermining Active NodesImplementation DetailsSlide 17PowerPoint PresentationEvaluation MethodologyResultsSlide 21Slide 22ConclusionsDiscussion: What about page replacement policies? Should (or how should) they be power-aware?Related WorkPower State TransitioningBenefit BoundarySlide 28Slide 29Dual-state HW Power State PoliciesQuad-state HW PoliciesPage Allocation and Power-Aware DRAMPage Allocation PolicesThe Design SpaceMethodologyMethodology ContinuedDual-state + Random Allocation (SPEC)Slide 41Results (Energy*Delay product)Quad-state HW (SPEC)Summary of Results (Energy*Delay product, RDRAM, ASPLOS00)Conclusion1ESSES 2003© 2003, Carla Schlatter EllisOutline for Today•Objective–Power-aware memory•AnnouncementsESSES 2003© 2003, Carla Schlatter EllisMemory System Power Consumption•Laptop: memory is small percentage of total power budget•Handheld: low power processor, memory is more importantMemoryOtherMemoryOtherLaptop Power Budget9 Watt ProcessorHandheld Power Budget1 Watt Processor3ESSES 2003© 2003, Carla Schlatter EllisOpportunity: Power Aware DRAM•Multiple power states–Fast access, high power–Low power, slow access•New take on memory hierarchy•How to exploit opportunity?Standby180mWActive300mWPower Down3mWNap30mWRead/WriteTransaction+6 ns+6000 ns+60 nsRambusRDRAM Power States4ESSES 2003© 2003, Carla Schlatter EllisRDRAM as a Memory Hierarchy•Each chip can be independently put into appropriate power mode•Number of chips at each “level” of the hierarchy can vary dynamically.ActiveNapPolicy choices–initial page placement in an “appropriate” chip–dynamic movement of page from one chip to another–transitioning of power state of chip containing pageActive5ESSES 2003© 2003, Carla Schlatter EllisCPU/$Chip 0Chip 1Chip 3RAMBUS RDRAM Main Memory DesignChip 2Part of Cache Block•Single RDRAM chip provides high bandwidth per access–Novel signaling scheme transfers multiple bits on one wire–Many internal banks: many requests to one chip•Energy implication: Activate only one chip to perform access at same high bandwidth as conventional designPower DownStandbyActive6ESSES 2003© 2003, Carla Schlatter EllisCPU/$Chip 0Chip 1Chip 3Conventional Main Memory DesignChip 2Part of Cache Block•Multiple DRAM chips provide high bandwidth per access–Wide bus to processor–Few internal banks•Energy implication: Must activate all those chips to perform access at high bandwidthActiveActive Active Active8ESSES 2003© 2003, Carla Schlatter EllisExploiting the OpportunityInteraction between power state model and access locality•How to manage the power state transitions?–Memory controller policies–Quantify benefits of power states•What role does software have?–Energy impact of allocation of data/text to memory.9ESSES 2003© 2003, Carla Schlatter EllisCPU/$OSPage MappingAllocationChip 0Chip 1Chip n-1Power DownStandbyActivectrl ctrl ctrlHardware controlSoftware control•Properties of PA-DRAM allow us to access and control each chip individually•2 dimensions to affect energy policy: HW controller / OS•Energy strategy:–Cluster accesses to already powered up chips–Interaction between power state transitions and data localityPower-Aware DRAM Main Memory Design10ESSES 2003© 2003, Carla Schlatter EllisPower-Aware Virtual Memory Based On Context SwitchesHuang, Pillai, Shin, “Design and Implementation of Power-Aware Virtual Memory”, USENIX 03.11ESSES 2003© 2003, Carla Schlatter EllisBasic Idea•Power state transitions under SW control (not HW controller)•Treated explicitly as memory hierarchy: a process’s active set of nodes is kept in higher power state•Size of active node set is kept small by grouping process’s pages in nodes together – “energy footprint” –Page mapping - viewed as NUMA layer for implementation–Active set of pages, i, put on preferred nodes, i•At context switch time, hide latency of transitioning–Transition the union of active sets of the next-to-run and likely next-after-that processes to standby (pre-charging) from nap–Overlap transitions with other context switch overhead12ESSES 2003© 2003, Carla Schlatter EllisCPU/$OSPage MappingAllocationChip 0Chip 1Chip n-1NapStandbyActivectrl ctrl ctrlHardware controlSoftware control•Properties of PA-DRAM allow us to access and control each chip individually•2 dimensions to affect energy policy: HW controller / OS•Energy strategy:–Cluster accesses to preferred memory nodes per process–OS triggered power state transitions on context switchPower-Aware DRAM Main Memory Design13ESSES 2003© 2003, Carla Schlatter EllisRambus RDRAMStandby225mWActive313mWPower Down7mWNap11mWRead/WriteTransaction+3 ns+22510 ns+20 nsRambusRDRAM Power States+20 ns+225 ns14ESSES 2003© 2003, Carla Schlatter EllisRDRAM Active ComponentsRefresh Clock RowdecoderColdecoderActiveX X X XStandbyX X XNapX XPwrdnX15ESSES 2003© 2003, Carla Schlatter EllisDetermining Active Nodes•A node is active iff at least one page from the node is mapped into process i’s address space.•Table maintained whenever page is mapped in or unmapped in kernel.•Alternativesrejected due to overhead:–Extra page faults–Page table scans •Overhead is onlyone incr/decrper mapping/unmapping opcountn0n1… n15p0108 2 17…pn193 240 432216ESSES 2003© 2003, Carla Schlatter EllisImplementation DetailsProblem: DLLs and files shared by multiple processes (buffer cache) become scattered all over memory with a straightforward assignment of incoming pages to process’s active nodes – large energy footprints afterall.17ESSES 2003© 2003, Carla Schlatter EllisImplementation DetailsSolutions:•DLL Aggregation–Special case DLLs by allocating Sequential first-touch in low-numbered nodes•Migration–Kernal thread – kmigrated – running in background when system is idle (waking up every 3s)–Scans pages used by each process, migrating if conditions met•Private page not on •Shared page outside i18ESSES 2003© 2003, Carla Schlatter Ellis19ESSES 2003© 2003, Carla Schlatter EllisEvaluation Methodology•Linux implementation•Measurements/counts taken of