Gate Interconnects and Delay Time Rise Time Delay Time and Slew Rate 1 Let Vs be the step voltage input and let Vo be the output voltage across the capacitor Vo Vs 1 exp t where RC The output voltage at the 10 50 and 90 points during the step is given by Vo 10 0 1Vs Vo 50 0 5Vs and Vo 90 0 9Vs Let the time at these points respectively be t10 t50 and t90 Therefore 0 1Vs Vs 1 exp t10 and 0 1 1 exp t10 So that 0 9 exp t10 Likewise 0 5 exp t50 and 0 1 exp t90 Taking the natural log of both sides of each of these equations and solving for the times we get 2 t10 ln 0 9 t50 ln 0 5 and t90 ln 0 1 The rise time is defined as tr t90 t10 Therefore tr ln 0 9 ln 0 1 ln 0 9 0 1 ln 9 2 20 Assuming that the input step rises instantaneously at t 0 the delay time p is simply t50 Therefore p ln 0 5 0 693 The slew rate SR is defined as the ratio of the voltage rise between the 10 and 90 points divided by the rise time Therefore SR 0 9Vs 0 1Vs tr 0 8Vs tr In summary for the RC Step Response tr 2 20 p 0 693 and SR 0 8Vs tr 3