1Gate Interconnects and Delay TimeRise Time, Delay Time, and Slew Rate2Let Vs be the step voltage input, and let Vo be the output voltage across thecapacitor:Vo = Vs(1-exp(-t/τ)), where τ = RC.The output voltage at the 10%, 50%, and 90% points during the step is given by:Vo(10%) = 0.1Vs, Vo(50%) = 0.5Vs, and Vo(90%) = 0.9Vs.Let the time at these points, respectively, be: t10, t50, and t90.Therefore, 0.1Vs = Vs(1-exp(-t10/τ)), and 0.1 = (1-exp(-t10/τ).So that 0.9 = exp(-t10/τ). Likewise, 0.5 = exp(-t50/τ) and 0.1 = exp(-t90/τ).Taking the natural log of both sides of each of these equations and solving for thetimes, we get:3t10 = -τln(0.9), t50 = -τln(0.5), and t90 = -τln(0.1).The rise time is defined as tr = t90 – t10. Therefore tr = τ(ln(0.9)-ln(0.1)) =τln(0.9/0.1) = τln(9) = 2.20τ.Assuming that the input step rises instantaneously at t = 0, the delay time (τp) issimply t50. Therefore, τp = -τln(0.5) = 0.693τ.The slew rate (SR) is defined as the ratio of the voltage rise between the 10% and90% points divided by the rise time.Therefore, SR = (0.9Vs – 0.1Vs)/tr = 0.8Vs/tr.In summary for the RC Step Response: tr = 2.20τ, τp = 0.693τ,and SR =