OutlinePolicies for Paged Virtual MemoryPage ReplacementTerminologyPage Reference StringExample (Artificially Small Pagesize)Example Reference StringAssessing Replacement AlgsManaging the VM Page CacheReplacement AlgorithmsExample: OptimalFIFOSlide 13LRUSlide 15LRU Approximations for PagingApproximations to LRUA Page Table Entry (PTE)Clock AlgorithmSlide 20Approximating a TimestampPractical ConsiderationsSlide 23The Paging DaemonFIFO with Second Chance (Mach)Illustrating FIFO-2CMMU GamesSlide 28Simulating Usage BitsCopy-on-WriteVariable / Global AlgorithmsVariable Space AlgorithmsWorking Set ModelSlide 34Slide 35Slide 36WSClockSlide 38ThrashingPros and Cons of VMMotivation: How to exploit remote memory?Distributed Shared Memory (DSM)DSM IssuesDSM StatesConsistency ModelsExample - the ProblemExample - Sequential ConsistencyExample - Weaker ConsistencyFalse SharingOutline•Objective for today: –Replacement policiesPolicies for Paged Virtual MemoryThe OS tries to minimize page fault costs incurred by all processes, balancing fairness, system throughput, etc.(1) fetch policy: When are pages brought into memory?•prepaging: reduce page faults by bring pages in before needed•on demand: in direct response to a page fault.(2) replacement policy: How and when does the system select victim pages to be evicted/discarded from memory?(3) placement policy: Where are incoming pages placed? Which frame?(4) backing storage policy:•Where does the system store evicted pages?•When is the backing storage allocated?•When does the system write modified pages to backing store?•Clustering: reduce seeks on backing storagePage Replacement•When there are no free frames available, the OS must replace a page (victim), removing it from memory to reside only on disk (backing store), writing the contents back if they have been modified since fetched (dirty).•Replacement algorithm - goal to choose the best victim, with the metric for “best” (usually) being to reduce the fault rate.Terminology•Each thread/process/job utters a stream of page references.–Model execution as a page reference string: e.g., “abcabcdabce..”•The OS tries to minimize the number of faults incurred.–The set of pages (the working set) actively used by each job changes relatively slowly.–Try to arrange for the resident set of pages for each active job to closely approximate its working set.•Replacement policy is the key.–Determines the resident subset of pages.Page Reference String1 0 1 0 01 0 1 0 11 0 1 1 01 0 1 1 11 1 0 0 01 1 0 0 1Addr trace Page str0 01 0 11 0 11 1 0AExample (Artificially Small Pagesize)#define dimint A[dim] [dim], B[dim] [dim];int main(){ int i, j, k;for (i= 0; i<dim; i++) for (j=0; j<dim; j++) B[i][j] = A[i][j]; exit;} ...sw $0,16($fp)$L10:lw $2,16($fp)slt $3,$2,dimbne $3,$0,$L13j $L11$L13:sw $0,20($fp)...BijExample Reference String…0 { 1 2 { 2 3 4 5 15 5 20 5 6}m 2 6 { 2 3 4 5 16 5 21 5 6}m 2 6 { 2 3 4 5 17 5 22 5 6}m 2 6 … { 2 3 4 5 19 5 24 5 6}m 2 6 7 }nABij131520Assessing Replacement AlgsModel program execution as a reference stringMetric of algorithm performance is fault rate•Comparison to base line of Optimal Algorithm.•For a specific algorithm: What is the information needed? How is that information gathered? When is it acted upon?•At each memory reference•At fault time•At periodic intervalsManaging the VM Page Cache1. Pages are typically referenced by page table entries.Must invalidate before reusing the frame.2. Reads and writes are implicit; the TLB hides them from the OS.How can we tell if a page is dirty?How can we tell if a page is referenced?3. Cache manager must run policies periodically, sampling page state.Continuously push dirty pages to disk to “launder” them.Continuously check references to judge how “hot” each page is.Balance accuracy with sampling overhead.Replacement AlgorithmsAssume fixed number of frames in memory assigned to this process:•Optimal - baseline for comparison - future references known in advance - replace page used furthest in future.•FIFO•Least Recently Used (LRU)stack algorithm - don’t do worse with more memory.•LRU approximations for implementationClock, Aging registerExample: Optimal…0 { 1 2 { 2 3 4 5 15 5 20 5 6}m 2 6 { 2 3 4 5 16 5 21 5 6}m 2 6 { 2 3 4 5 17 5 22 5 6}m 2 6 … { 2 3 4 5 19 5 24 5 6}m 2 6 7 }nABijVAS01234515206 3415202 131520FIFO•No extra hardware assistance needed, No per-reference overhead (we have no information about actual access pattern)•At fault time: maintain a first-in first-out queue of pages resident in physical memory•Replace oldest resident page•Why it might make sense - straight-line code, sequential scans of data•Belady’s anomaly - fault rate can increase with more memoryExample Reference String…0 { 1 2 { 2 3 4 5 15 5 20 5 6}m 2 6 { 2 3 4 5 16 5 21 5 6}m 2 6 { 2 3 4 5 17 5 22 5 6}m 2 6 … { 2 3 4 5 19 5 24 5 6}m 2 6 7 }nABij0 1 23 4515 2062131520LRU•At fault time: replace the resident page that was last used the longest time ago•Idea is to track the program’s temporal locality•To implement exactly: we need to order the pages by time of most recent reference (per-reference information needed  HW, too $$)–timestamp pages at each ref, stack operations at each ref•Stack algorithm - doesn’t suffer from Belady’s anomaly -- if i > j then set of pages with j frames is a subset of set of pages with i frames.…0 { 1 2 { 2 3 4 5 15 5 20 5 6}m 2 6 { 2 3 4 5 16 5 21 5 6}m 2 6 { 2 3 4 5 17 5 22 5 6}m 2 6 … { 2 3 4 5 19 5 24 5 6}m 2 6 7 }n5Example Reference String0120123344515202015155205 6 6LRU Approximations for Paging•Pure LRU and LFU are prohibitively expensive to implement.–most references are hidden by the TLB–OS typically sees less than 10% of all references–can’t tweak your ordered page list on every reference•Most systems rely on an approximation to LRU for paging.–Implementable at reasonable cost –periodically sample the reference bit on each page•visit page and set reference bit to zero•run the process for a while (the reference window)•come back and check the bit again–reorder the list of eviction candidates based on samplingApproximations to LRU•HW support: usage/reference bit in every PTE - set on each reference. –Set in TLB