Outline for TodayCPS 104++: Almost Everything You Wanted to Know About Operating System’s Interaction with Architecture but were Afraid to AskWhat does an OS do?OS Services: I/OBasic Storyline – Evolution of HW SupportThe Big PictureSystem OrganizationSlide 8Slide 9What do we need to know about the Processor?A "Typical" RISC ProcessorExecuting a ProgramAn Abstract View of the ImplementationProgram StackSlide 15Interrupts are a Key MechanismRole of Interrupts in I/OInterrupts and ExceptionsCPU handles interruptAn Execution ContextHandling an Interrupt/ExceptionContext SwitchesCrossing Protection BoundariesA System CallUser / Kernel ModesExecution ModeCPU Handles Interrupt (with User Code)Multiple User ProgramsCPU Handles Interrupt (Multiple Users)Timer OperationIssues of Sharing Physical MemorySharing Physical MemoryMemory Hierarchy 101Slide 34Role of MMU Hardware and OSVirtual Address TranslationPage Table MappingConcurrencyThe Trouble with ConcurrencySolution: Atomic Sequence of InstructionsHW Support for Atomic OperationsSummaryOutline for Today•Announcements–Those who didn’t get your photo taken last time, you can provide a picture – jpg, 216x216 px–Groups - if you haven’t sent me email DO IT Today by 8pm! After that, I’ll assign the rest of you into groups.–If you weren’t here last time, fill out who’s who questionnaire (doc format on the web page).–Plug for Soph. and Juniors to do undergrad research experiences - CRA awards•Objective of Today’s Lecture:Review of computer architectureCPS 104++:Almost Everything You Wanted to Know About Operating System’s Interaction with Architecture but were Afraid to AskNeedCPS 110 3Alvin R. Lebeck3What does an OS do?•Manipulate and Control Programs–Place and remove them from memory (treat as data)–Start them, “Freeze” (stop) them, “thaw” (restart) them–Set Memory management hardware to monitor their use of memory•Need to know (from 104)–Programs consist of instructions, each a “word” (32 bits on MIPS)–Programs and data reside in memory–Memory is an array of bytes (2^32 on MIPS)–Program, and data structures reside in “blocks” of memory (sequentially addressed bytes) (a byte is 8 bits; 4 bytes per word–To freeze a program, stop its execution, and save its “state”»State: all registers, memory, status flags, mode bit, memory management tables, interrupt status bits that the program can access, or which affect how the program executes indirectlyCPS 110 4Alvin R. Lebeck4OS Services: I/O•OS provides I/O device ABSTRACTIONS to programs–Files–Communication channels•You need to know–Something about the underlying I/O hardware»Disks•Large number of addressable records, each holding maybe 8K bytes•Records placed on disk in concentric tracks, on many physical surfaces–Seek to move arm to proper “cylinder”–Wait while proper record spins under R/W head–Use electronics to select which surface to Read/Write–Must operate on whole record•OS defines logical structure on top of this, to present file abstractionBasic Storyline – Evolution of HW Support•The bare machine: instruction cycle, register state, DMA I/O, interrupts.•Add an OS, to safely and efficiently start and execute user programs •But user programs might damage the OS–better restrict user code from having direct access to (at least) I/O»Need: protected instructions, kernel/user modes, system calls.•Add sharing among multiple users–Need: memory protection, timers, instructions to assist synchronization, process abstraction.The Big PictureMemoryControlDatapathProcessorInputOutput•The Five Classic Components of a Computer Von Neumann machineI/O BusMemory BusProcessorCacheMainMemoryDiskControllerDisk DiskGraphicsControllerNetworkInterfaceGraphicsNetworkinterruptsSystem OrganizationI/O BridgeI/O BusMemory BusProcessorCacheMainMemoryDiskControllerDisk DiskGraphicsControllerNetworkInterfaceGraphicsNetworkinterruptsSystem OrganizationI/O Bridge MemoryhierarchyI/O BusMemory BusProcessorCacheMainMemoryDiskControllerDisk DiskGraphicsControllerNetworkInterfaceGraphicsNetworkinterruptsSystem OrganizationI/O Bridge I/OWhat do we need to know about the Processor?•Size (# bits) of effective memory addresses that can be generated by the program and therefore, the amount of memory that can be accessed.•Information that is crucial: process state or execution context describing the execution of a program (e.g. program counter, stack pointer). This is stuff that needs to be saved and restored on context switch. •When the execution cycle can be interrupted.What is an indivisible operation in given architecture?A "Typical" RISC Processor•32-bit fixed format instruction•32 (32,64)-bit GPR (general purpose registers)•32 Floating-point registers(not used by OS, but part of state)•Status registers (condition codes)•Load/Store Architecture–Only accesses to memory are with load/store instructions–All other operations use registers–addressing mode: base register + 16-bit offset•Not Intel x86 architecture!Executing a Program•Thread of control (program counter)•Basic steps for program execution(execution cycle)–fetch instruction from Memory[PC], decode it–execute the instruction (fetching any operands, storing result, setting condition codes, etc.)–increment PC (unless jump)An Abstract View of the ImplementationClk5Rw Ra Rb32 64-bitRegistersRdALUClkDataInDataOutDataAddressIdealDataMemoryInstructionInstruction AddressIdealInstructionMemoryClkPC5Rs5Rt16Imm32323232ABSimplistic…Program Stack•Some known register is stack pointer•Stack is used for–passing parameters (function, method, procedure, subroutine)–storing local variablesLocal variablesReturn resultsReturn AddressOld frame ptrarg1arg2A stack frame (Activation Record)Frame 0Frame 1Frame 2Frame ptrstack ptrFirst few return results and arguments can be passed in specific registers(calling conventions)What do we need to know about the Processor?Size (# bits) of effective memory addresses that can be generated by the program and therefore, the amount of memory that can be accessed.Information that is crucial: process state or execution context describing the execution of a program (e.g. program counter, stack pointer). This is stuff that needs to be saved and restored on context switch. •When the execution cycle can be interrupted.What is an indivisible operation in given architecture?Interrupts are a