1ECET 331 – Digital Integrated CirciutsChapter 8Introduction to Sequential LogicECET 331Digital Integrated CircuitsSequential Circuitz A digital circuit whose output depends not only on the present combination of input, but also on the history of the circuitz The circuit has elements of memoryECET 331Digital Integrated CircuitsSequential Circuit Elementsz 2 basic types• Latch• Flip-flopz Different conditions under which a stored bit changes ECET 331Digital Integrated CircuitsSequential Circuit Inputsz SET• Makes the device store a logic 1z RESET• Makes the device store a logic 0z SET and RESET may be active high or active lowECET 331Digital Integrated CircuitsSequential Circuit Outputsz Two complementary outputs• Q• !Q (or Q-bar)z These outputs are always in opposite logic statesECET 331Digital Integrated CircuitsSR Latch2ECET 331Digital Integrated CircuitsWorks like a Push-Button Start / Stopz Push the start button to start a motorz Push it again, motor continues to runz Push stop to stop the motorz Push stop again, nothing happensz Push stop and start together?STOPSTARTECET 331Digital Integrated CircuitsSequential Circuit Statesz A device is set or on when• Q = 1 and !Q = 0z A device is reset or off when• Q = 0 and !Q = 1 ECET 331Digital Integrated CircuitsNOR Latch Implementationz Truth TableS R Action0 0 Output does not change0 1 Output is RESET1 0 Output is SET1 1 Forbidden conditionECET 331Digital Integrated CircuitsNAND Latch Implementationz Truth Table!S !R Action0 0 Forbidden condition0 1 Output is SET1 0 Output is RESET1 1 Output does not changeECET 331Digital Integrated CircuitsLatch Operationz 2 possible stable states• Set• Resetz Feedback keeps the latch in one of these stable states until the inputs changeECET 331Digital Integrated CircuitsLatch Circuit Diagrams3ECET 331Digital Integrated CircuitsNAND Latch Function Table!S !R Qt+1 !Qt+1 Function0 0 1 1 Forbidden0 1 1 0 Set1 0 0 1 Reset0 0 Qt !Qt No ChangeECET 331Digital Integrated CircuitsFunction Table Notationz Qt• Indicates the present state of the Q outputz Qt+1• Indicates the next state of the Q output after the specified inputs are appliedECET 331Digital Integrated CircuitsSwitch Bouncez The condition where the closure of a switch contact results in a mechanical bounce before the final contact is madez In logic circuits, this causes several pulses instead on one on the switch closureECET 331Digital Integrated CircuitsSwitch Debounce Circuitz Uses a NAND latch with switch contacts connected to +5 voltsz Bounce is ignored since that condition results in inputs of S =1, R = 1 (a no-change condition)ECET 331Digital Integrated CircuitsSwitch Debounce CircuitECET 331Digital Integrated CircuitsGated SR Latchz The time when a latch is allowed to change state is regulatedz Change of state is regulated by a control signal called ENABLEz Circuit is a NAND latch controlled by steering gates4ECET 331Digital Integrated CircuitsGated SR Latch Circuitz 2 uses• ON / OFF signal (enables or disables the latch)• SynchronizerECET 331Digital Integrated CircuitsGated SR Latch Function TableEN S R Qt+1 !Qt+1 Function1 0 0 Qt !Qt No change1 0 1 0 1 Reset1 1 0 1 0 Set1 1 1 0 0 Forbidden0 X X Qt !Qt InhibitedECET 331Digital Integrated CircuitsGated D (or Transparent) Latchz A latch whose output follows its data input when its ENABLE input is activez When ENABLE is inactive, the latch stores the data that was present when ENABLE was last activeECET 331Digital Integrated CircuitsTransparent Latch Function TableEN D Qt+1 !Qt+1 Function0 X Qt !Qt No change, store1 0 0 1 Reset (transparent)1 1 1 0 Set (transparent)ECET 331Digital Integrated CircuitsD Latches in Quartus IIz Can be implemented as a primitive in a Block Design File (.bdf)z Can be implemented with a behavioral or structural description in a VHDL fileECET 331Digital Integrated CircuitsVHDL Implementation of a D LatchENTITY d_latch ISPORT (d, ena : IN BIT;q : OUT BIT);END d_latch;ARCHITECTURE behavioral OF d_latch isBEGINPROCESS (d, ena)BEGINIF (ena = ‘1’) THENq <= d;END IF;END PROCESS;END behavioral;5ECET 331Digital Integrated CircuitsVHDL PROCESS Statementz PROCESS statement is concurrent with other statements• Executes (Fires) when any signal in the sensitivity list changesz Statements inside the PROCESS are sequentialECET 331Digital Integrated CircuitsVHDL Implementation of Latches with Multiple Inputs / Outputs and a Common Enablez 3 approaches• Use a behavioral description (as we just did) with STD_LOGIC_VECTOR types rather than single bits• Use a latch primitive (predefined component) instantiated with a GENERATE statement• Use a component from a library of parameterized modules (LPM) with GENERIC mapsECET 331Digital Integrated CircuitsBehavioral DescriptionLIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY latch_4 ISPORT (d : IN STD_LOGIC_VECTOR(3 DOWNTO 0);enable : IN STD_LOGIC;q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END latch_4;ARCHITECTURE behavioral OF latch_4_behav ISBEGINPROCESS (enable, d)BEGINIF (enable = ‘1’) THENq <= d;END PROCESSEND behavioral;ECET 331Digital Integrated CircuitsPrimitives with GENERATELIBRARY ieee;USE ieee.std_logic_1164.ALL;LIBRARY altera;USE altera.maxplus2.ALL;ENTITY latch_4 ISPORT (d_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);enable : IN STD_LOGIC;q_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END latch_4;ARCHITECTURE with_generate OF latch_4_prim ISBEGIN-- Instantiate a latch from a Max+PlusII primitivelatch4:FOR i IN 3 DOWNTO 0 GENERATElatch_primitive: latchPORT MAP ( d => d_in(i), ena => enable, q => q_out(i) );END GENERATE;END with_generate;ECET 331Digital Integrated CircuitsParameterized ModuleLIBRARY ieee;USE ieee.std_logic_1164.ALL;LIBRARY lpm;USE lpm.lp_components.ALL;ENTITY latch_4 ISPORT (d_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);enable : IN STD_LOGIC;q_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END latch_4_prim;ARCHITECTURE with_param OF latch_4 ISBEGIN-- Instantiate a latch from an LPM_componentlatch4: lpm_latchGENERIC MAP (LPM_WIDTH => 4)PORT MAP ( d => d_in, ena => enable, q => q_out );END with_param;ECET 331Digital Integrated CircuitsFlip-Flopz A gated latch with a clock inputz The sequential circuit output changes when its CLOCK input detects an edgez Edge-sensitive