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1ECET 331 – Digital Integrated CircuitsChapter 10State Machine DesignECET 331Digital Integrated CircuitsTermsz State Machine• A synchronous sequential circuit consisting of a sequential logic section (flip-flops) and a combinational logic section• The outputs of internal flip-flops progress through a predictable sequence of states according to:z A clockz Their present statesz Other control inputsECET 331Digital Integrated CircuitsTermsz Moore Machine• A Finite State Machine (FSM) whose outputs are determined only by the Sequential Logic (FFs) state of the FSMz Mealy Machine• A FSM whose outputs are determined by both the Sequential Logic and Combinational Logic of the FSM• Outputs can change asynchronouslyECET 331Digital Integrated CircuitsTermsz State variables• The (Q) outputs held by the flip-flops of a state machine that determine its present state• The number of flip-flops of a state machine is equivalent to the number of state variablesz A FSM has:• A memory section that holds the present state of the machine (stored in FF) and • A control section that determines the next state of the machine (by clocks, inputs and present state)ECET 331Digital Integrated CircuitsMoore-Type State MachineControlSection(Gates)MemorySection(Flip-flops)InputsCommandLinesStatus LinesOutput Decoder(optional)OutputsCLKStores present state“Less is Moore”Determines next stateECET 331Digital Integrated CircuitsMealy-Type State MachineControlSection(Gates)MemorySection(Flip-flops)InputsCommandLinesStatus LinesOutputsCLKStores present stateDetermines next state2ECET 331Digital Integrated CircuitsState Machine Examplesz Simple:• Countersz Complex:• Microprocessor instruction decoder and sequencerECET 331Digital Integrated CircuitsFSM Design Techniquesz Classical Design• Makes use of State Tables, FF Excitation Tables, and Karnaugh Mapping to find FF Input Control Logic• Similar to the process for counter designz VHDL Design• Uses CASE statements or IF THEN ELSE statements to capture the design and Logic Synthesis Tools to define equationsECET 331Digital Integrated CircuitsClassical Design Approach1. Define the actual Problem2. Draw a State (Bubble) Diagram to implement the problem3. Make a State Table• In the state table define all present states and inputs in an incrementing binary sequence• Then define the Next States and Outputs (from State Diagram)ECET 331Digital Integrated CircuitsClassical Design Approach4. Use FF Excitation Tables to determine what states the FF synchronous inputs must be at to cause the desired Present State to Next State Transition5. Write the Output Values for each Present State/Input combination6. Simplify Boolean Expression for each FF input and Output Equation 7. Draw the required logic circuitECET 331Digital Integrated CircuitsFSM Design Examplez Gray Code Counter that sequences {000, 001, 011,010,110,111,101,100,000}z From this the state table is developed for D Flip FlopsECET 331Digital Integrated CircuitsGray Code Counter State DiagramMealy or Moore? S0000S7100S1001S20011S3010S4110S5111S61013ECET 331Digital Integrated CircuitsD Flip-Flop Excitation TableTransition D===============0 Æ 0 00 Æ 1 11 Æ 0 01 Æ 1 1ECET 331Digital Integrated CircuitsGray Code Counter State TablePresent State Next State Synchronous InputsQ2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0===================================================0 0 0 0 0 1 0 0 10 0 1 0 1 1 0 1 10 1 0 1 1 0 1 1 00 1 1 0 1 0 0 1 01 0 0 0 0 0 0 0 01 0 1 1 0 0 1 0 01 1 0 1 1 1 1 1 11 1 1 1 0 1 1 0 1Note: Incrementing OrderECET 331Digital Integrated CircuitsGray Code Counter Boolean Equationsz Reduce State Table synchronous inputs using K-mapsD2 <= (Q1 and (not Q0)) or (Q2 and Q0);D1 <= (Q1 and (not Q0)) or ((not Q2)and Q0);D0 <= ((not Q2) and (not Q1)) or (Q2 and Q1);ECET 331Digital Integrated CircuitsGray Code Counter K-mapsECET 331Digital Integrated CircuitsVHDL FSM Designz Uses an Enumerated Type to declare State Variablesz Enumerated Type• A user defined type in which all possible values of a named identifier are listed in a Type Definition• Doesn’t say anything about the output valuez A FSM uses a CASE Statement on the Enumerated Type State VariableECET 331Digital Integrated CircuitsVHDL Gray Code Counter EntityENTITY gray_ctl ISPORT ( clk : IN STD_LOGIC;q : OUT STD_LOGIC_VECTOR(7 downto 0));END gray_ctl;4ECET 331Digital Integrated CircuitsVHDL Gray Code Counter ArchitectureARCHITECTURE a OF gray_ctl ISTYPE STATE_TYPE IS (s0,s1,s2,s3,s4,s5,s6,s7);SIGNAL state :STATE_TYPE;BEGINPROCESS (clk)BEGINIF (clk’EVENT AND clk = ‘1’) THENCASE state ISWHEN s0 => state <= s1;WHEN s1 => state <= s2;WHEN s2 => state <= s3;WHEN s3 => state <= s4;WHEN s4 => state <= s5;WHEN s5 => state <= s6;WHEN s6 => state <= s7;WHEN s7 => state <= s0;END CASE;END IF;END PROCESS;ECET 331Digital Integrated CircuitsOutput AssignmentsWITH state SELECTq <= “000” WHEN s0;q <= “001” WHEN s1;q <= “011” WHEN s2;q <= “010” WHEN s3;q <= “110” WHEN s4;q <= “111” WHEN s5;q <= “101” WHEN s6;q <= “100” WHEN s7;END a;-- Note the Output Assignments are made outside of the-- Process Concurrently (this is the output decode-- block)ECET 331Digital Integrated CircuitsOutput Assignments (Alternative)z The Output Assignment for the proceeding example could have also been in the CASE test Statements (in the Process)WHEN s0 => state <= s1;q <= “001”;WHEN s1 => state <= s2;q <= “011”;ECET 331Digital Integrated CircuitsFSM with Control Inputsz Same design approach as we used with FSMssuch as countersz Uses the Control Inputs and Clock to Control the sequencing from state to statez Outputs will not necessarily be the same as the output states of the machine’s FFs• More detailed state diagram notation neededECET 331Digital Integrated CircuitsState Diagram NotationHow many FFs are needed to implement this machine?ECET 331Digital Integrated CircuitsFSM Diagram Notationz Bubbles contain the State Name and Value (StateName/Value) such as Start/000• “Value” denotes collective values of state variablesz Transitions between states are designated with arrows from one bubble to anotherz Each transition has an ordered Input/Output label such as IN1/OUT1• Called a “Legend”5ECET 331Digital Integrated CircuitsFSM Diagram Notationz So, if


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WCU ECET 331 - State Machine Design

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