+15V+Vin-+VOUT-RLRG++[a] Common Source Amplifier [b] Common Drain [Source Follower] AmplifierRSRS+15V+Vin-+VOUT-RL++[c] Common Gate AmplifierJFET AMPLIFIER CONFIGURATIONS+15VR G+Vin-+VOUT-RS++Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007.MITOpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].RG+15VIDRL+Vout_+JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITSRi+Vi_RiRLgmVgs+Vout_+Vi_2N5459RSgsg ds+Vgs_RSdCOMMON SOURCE AMPLIFIER WITH BYPASSED SOURCE RESISTOR []LmvSmLmvSmgsLgsmSgsmgsLgsminoutvRgAorRgRgARgvRvgRvgvRvgvvA−=+−=+−=+−==11 2 9/27/06Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].RG+15VID+Vout_+JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITSRi+Vi_RigmVgs+Vout_+Vi_2N5459RSgg+Vgs_RSddsCOMMON DRAIN [SOURCE FOLLOWER] AMPLIFIERs []SmSmvSmgsSgsmSgsmgsSgsminoutvRgRgARgvRvgRvgvRvgvvA+=+=+==1;1 3 9/27/06Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].+15VIDRL d+Vout_+JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS+Vi_RiRLgmVgs+Vout_+Vi_ 2N5459RSgds_Vgs+RSCOMMON GATE AMPLIFIERsRig 4 9/27/06Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].LmviSiimLmSiimgsLgsminoutRgARRRRgRgRRRgvRvgvvthenifvA==++=++−−==⎥⎦⎤⎢⎣⎡,;110 5 9/27/06Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 02139 Low Frequency Hybrid-π Equation Chart TRANSISTORS Characteristic Common Emitter CE with RE CC [E. Follower] Common Base Voltage Gain [if ro >>RL] LmvRgA −= ELvRRA −≈ 1≈vA ()soELovRRrRA1// ++=ββπ Current Gain βo βo βo+1 1+ooββ Input Impedance BRr //π ()[]BEoRRr //1++βπ()[]BEoRRr //1++βπ 1+orβπ Output Impedance RL [if ro >>RL] RL [if ro >>RL] ()EoBsRRRr//1//⎥⎦⎤⎢⎣⎡++βπ RL [if ro >>RL] Phase Reversal? Yes Yes No No JFET’S Characteristic Common Source C Source with RS Common Drain [Source Follower] Common Gate Voltage Gain [if rds >>RL] LmvRgA −= SmLmvRgRgA+−=1 SmSmvRgRgA+=1 SiimLmvRRRgRgA++=1 Ri = generator resistance Current Gain SDII Very large! SDII Very large! SDII Very large! 1+=SmSmiRgRgA Input Impedance RG RG RG SmSmSRgRgR//11=+Output Impedance RL [if rds >> RL] RL [if rds >> RL] SmSmSRgRgR//11=+ RL [if rds >>RL] Phase Reversal? Yes Yes No No 6 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].FET COMMON-SOURCE AMPLIFIER BIASING-GRAPHICAL METHOD #1 1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER. [VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0] 2. ASSUME RS << RL. 3. PLOT A LOAD LINE ON THE OUTPUT CHARACTERISTICS. KEEP THE ID , VDS = 0 INTERCEPT ON THE GRAPH PAGE; I. E. STAY AWAY FROM NEARLY VERTICAL LOAD LINES. 4. CALCULATE RL FROM THE LOAD LINE INTERCEPTS. USE CLOSEST STD. VALUE. 5. PICK Q-POINT VALUE OF VGS FOR MAXIMUM LINEAR OUTPUT SWING. 6. CALCULATE ID: 2)off(GSGSDSSDVV1II⎟⎟⎠⎞⎜⎜⎝⎛−=; OR ESTIMATE FROM CHARACTERISTICS. 7. CALCULATE RS FOR VGS AT ID . RVISGSD=⎛⎝⎜⎞⎠⎟. USE CLOSEST STANDARD VALUE. 8. COMPARE RS AND RL ; IF RS IS CLOSE TO RL , REPLOT THE LOAD LINE. 9. RECALCULATE RS FOR NEW VGS . REPEAT STEPS 7 AND 8 AS NECESSARY! CALCULATING JFET SMALL-SIGNAL gm 1. CALCULATE gm FROM ΔID /ΔVGS ON DRAIN CHARACTERISTICS FROM CURVE TRACER [LARGE SIGNAL gm ] 2. OR USE MEDIAN SPECIFICATION SHEET VALUE. [FOR A FAST ESTIMATE.] OR DSSD)off(GSDSS)off(GSGS)off(GSDSSmIIVI2VV1VI2g−=⎟⎟⎠⎞⎜⎜⎝⎛−−= WHERE VGS or ID = OPERATING POINT. When VGS = VGS(OFF), ID = 0 ; IDSS = ID @ VGS = 0. NOTE THAT THE SMALL-SIGNAL TRANSCONDUCTANCE DEPENDS ON THE DC BIAS POINT, JUST AS IT DOES FOR THE BIPOLAR TRANSISTOR! 7 9/27/06Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].FET COMMON-SOURCE AMPLIFIER BIASING-GRAPHICAL METHOD #2 1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER. [VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0] 2. REFER TO THE COMBINED TRANSFER [TRANSCONDUCTANCE] CHARACTERISTICS AND DRAIN CHARACTERISTICS CURVES [ATTACHED]. 3. CHOOSE RS AS FOLLOWS: DSS)OFF(GSSIVR =. DRAW THE LINE REPRESENTING RS FROM THE ORIGIN OF THE TRANSFER CURVE GRAPH; THE “Q” POINT IS AT THE INTERSECTION OF THE TWO PLOTS. THIS SETS IDQ AT ABOUT 0.4 IDSS. 4. EXTEND A HORIZONTAL LINE FROM THE IDQ VALUE ON THE TRANSFER CHARACTERISTICS’ LEFT-HAND AXIS ALL THE WAY ACROSS THROUGH THE DRAIN CHARACTERISTICS. 5. THE RIGHT-HAND VOLTAGE INTERCEPT FOR THE LOAD LINE [ON THE DRAIN CHARACTERISTICS] IS EQUAL TO THE SUPPLY VOLTAGE VDD. CHOOSE A VALUE FOR VDSQ THAT GIVES A ROUGHLY SYMMETRICAL OUTPUT VOLTAGE SWING AROUND VDSQ. 6. DRAW A VERTICAL LINE FROM VDSQ UPWARDS TO INTERSECT WITH THE LINE DRAWN IN STEP #4. THIS INTERSECTION GIVES THE Q-POINT. 7. DRAW THE LOAD LINE FROM THE SUPPLY VOLTAGE THRU THE Q-POINT UNTIL IT INTERSECTS WITH THE CURRENT AXIS. 8. DIVIDE THE SUPPLY VOLTAGE BY THE CURRENT AXIS VALUE TO GET THE TOTAL VALUE OF RESISTANCE IN THE DRAIN-SOURCE CIRCUIT. 9. SUBTRACT THE VALUE OF RS FOUND IN STEP #3 FROM THE VALUE FOUND IN STEP #8 TO GET THE VALUE OF LOAD [OR DRAIN] RESISTOR. USE CLOSEST STANDARD VALUE FOR BOTH RESISTORS. 10. NOTE THAT THE MORE VERTICAL THE LOAD LINE, THE SMALLER THE VALUE OF RL. LOW RL EQUALS LOW VOLTAGE GAIN [AV = - gmRL]. ACCEPTING A LOWER VOLTAGE VDQ WITH ITS