Last Time Making correct concurrent programs Maintaining invariants Avoiding deadlocksToday Power management Hardware capabilities Software management strategiesPower and Energy Review Energy is power integrated over time 1 Watt == 1 Joule / second Heat depends on power consumptionBattery life depends on energy consumptionBattery life depends on energy consumption Both power and energy consumption must be boundedThe Power Problem Processors are getting faster but using more power Performance / Watt remains low Battery capacities increase slowly Solutions: Use a better VLSI process Have the system do less work Spread work across several smaller, slower processors Push the problem to the user• New cell phones often have worse lifetime than the previous generation• Most users choose features over lifetime! Use power management techniquesBatteries Usable energy density increasing by ~10% / year Dominant rechargeable battery technology where energy density is important: Lithium-ion 110-160 Wh/KG About 1/3 the energy density of dynamite! In contrast… Gasoline: 14,000 Wh/Kg Hydrogen: 38,000 Wh/KgCMOS Power Consumption Affected by: Voltage• Power consumption proportional to V2 Toggling• More activity == more powerLeakageLeakage• Idle components draw powerPower Saving Features Voltage Reduce power supply voltage Toggling Reduce activity Use simpler hardwareThese necessitate clock speed reductionsThese necessitate clock speed reductions Leakage Disconnect inactive parts from power supplyClock Gating Applicable to processors, memories, etc Not analog components Disconnect parts from clock when not in use Stops signal propagation Pros: Simple Fast – Stopping only clock distribution, not clock generation Cons: Clock still runs, using power Does not prevent leakageSupply Shutdown Disconnect parts from power supply when not in use Pros: General Saves the most power Con: Long transition timeExample: Intel SA-1100 StrongARM variant for PDA-type devices Small I- and D-caches Runs up to 200 MHz Three power modes Run – normal operationIdle –stops processor clock, I/O logic still poweredIdle –stops processor clock, I/O logic still powered Sleep – most chip activity shut downSA-1100 Sleep Run → Sleep 30 µs – Flush CPU state to RAM 30 µs – Reset processor state 30 µs – Shut down clock Sleep → Run10 ms –Ramp up power supply10 ms –Ramp up power supply 150 ms – Stabilize clock Small – Boot CPUSA 1100 Transition CostsRunP = 400 mW90 us160 ms10 us10 us Power consumption during transition = PrunSleepIdleP = 50 mW P = 0.16 mW90 us160 ms10 us90 usMCF5223x Power Most peripherals can be independently powered down CPU modes: run, wait, doze, stop STOP instruction puts a running processor into one of the three power-saving modes•Which one depends on contents of LPCR•Which one depends on contents of LPCR Interrupt can bring the CPU out of wait, doze, and stop No recovery time to bring CPU, SRAM, and flash out of any power saving mode• PLL continues to run in all three modesMore MCF5223x Run mode – 75-290 mA @ 25 MHz Wait mode – 16 mA CPU and memory clocks are stopped Peripherals continue to operate normally Doze mode – 16 mA Some peripherals are stopped, others keep running Stop mode – 0.2-10 mA All clocks stopped – peripherals do not operate Only external interrupts can wake the processorMeeting Power Goals What do you look for in a platform? How do you know if a system built on it can meet your goals?Power Management Policies Static power management – Does not depend on system activity E.g., user-initiated suspend, hibernate, etc. Dynamic power management – Automatically take actions based on system activityactions based on system activity E.g. shut down functional units, change CPU frequencyDynamic Power Management Goal Appropriately trade off between performance and power consumption Basic premisesSystems have non-uniform workloadsSystems have non-uniform workloads It is possible to predict fluctuation in workload with some degree of accuracy• E.g., “the CPU was very busy for the past 1 ms, so it will probably remain busy for the next 1ms”Problem Formulations Need to figure out what the goal is For example: Minimize power under performance constraints• E.g. must not skip frames while playing MP3 or DVD Maximize performance under power constraints•E.g. battery must last for the entire plane flight•E.g. battery must last for the entire plane flightBaseline Policy: Greedy Immediately sleep or idle the processor when there’s no work to do Works well when transition times are short compared to idle periods Works poorly when transition times are relatively long•I.e., Run/Sleep transitions for the SA-1100•I.e., Run/Sleep transitions for the SA-1100 Need to do better than this…Break-Even Time TBE Minimum idle time needed to make up for the cost of entering a sleep mode Only beneficial to sleep the CPU if the idle time is longer than thisAssume for now that…Assume for now that… No performance penalty is tolerated We know in advance the duration of idle periodsBreak-Even Time PTR: Power consumption during transition POn: Power consumption when active Assume PTR≤ POnTBEof an inactive state is the total time for entering TBEof an inactive state is the total time for entering and leaving the state TBE= TTR= TOn,Off+ TOff,On Example: TBE= 160 ms + 90 µs for SLEEP in SA-1100How to Save Energy Given an idle period Tidle> TBE Saved energy = (Tidle- TTR)(POn- POFF) + TTR(POn– PTR) Total energy that can be saved depends on distribution and size of idle timesdistribution and size of idle timesPower Saved On real-world tracesDynamic Voltage Scaling Power is proportional to V2 Reduce power supply voltage → Save energy Lower voltage necessitates reduced clock frequency So we can trade off performance and lifetime on a set of batteriesbatteries Why dynamic? Observation: Often, peak CPU requirement >> average CPU requirement So: Run fast when we have to, run slow otherwiseMore DVS Changing voltage takes time To stabilize power supply and clock