Architecture L3 - DevicesD Flip-FlopREGISTERMEMORYSlide 5Kennesaw State UniversityE X C E E D I N G E X P E C T A T I O N SArch L3CSIS 3510 Computer Organization and ArchitectureDr. HogansonArchitecture L3 - DevicesThis next level uses the ideas from previous levels and builds more complex constructions, using abstraction and encapsulation.Example: Register•Register is a storage unit within the CPU (Central Processing Unit) chip•It can store one word of memory•PCs are 32-bit machines (4 bytes per word)•Earlier machines were 8-bit and 16-bit. Coming: 64-bit (8 bytes)•The computer manipulates and works with words of storage (more later)Kennesaw State UniversityE X C E E D I N G E X P E C T A T I O N SArch L3CSIS 3510 Computer Organization and ArchitectureDr. HogansonD Flip-Flop•The memory device we have considered is a “D” latch.•“D” for Data, holds or latches one bit•D flip-flop adds to the D-latch for better control (skip details)•Black-Box abstraction of a D flip-flop–Control determines read or write–New input on input–See contents on output DINPUTOUTPUTCONTROLKennesaw State UniversityE X C E E D I N G E X P E C T A T I O N SArch L3CSIS 3510 Computer Organization and ArchitectureDr. HogansonREGISTER•Group multiple D flip-flops together to form a register.•Connect all control lines together, so all operate at same timeCONTROLD I2D I1D I3D I0 O0 O1 O2 O3•Parallel INPUT and OUTPUT•WORD: multiple Ds (this example is 4 bit word size)Kennesaw State UniversityE X C E E D I N G E X P E C T A T I O N SArch L3CSIS 3510 Computer Organization and ArchitectureDr. HogansonMEMORY•One way to view MEMORY is as a bank of REGISTERSAddress0123INPUTOUTPUTKennesaw State UniversityE X C E E D I N G E X P E C T A T I O N SArch L3CSIS 3510 Computer Organization and ArchitectureDr. HogansonMEMORY•Control is through addresses •Input and Output on Buses (multiple parallel wires)•word size determines bus size•Memory access cycle (read)–CPU places address needed on bus–Memory latches (aquires) the address–Memory uses address to produce data–Memory outputs data to bus–CPU latches data from bus•Number of words needed determines the number of “registers”, and the number of address lines needed on the bus•Size of “register” (word) determines the number of bus lines needed for input data and output data, to and from