CSIS 3510 Computer Organization and ArchitecturePowerPoint PresentationSolve the S=R=1 problemAnother S-R FFPackaging D Gates in ChipsPackaging D gates4 X 3 MemoryAlternative Memory OrganizationMemory Design ProblemSlide 10Slide 11CSIS 3510Dr. HogansonMemory ConstructionCSIS 3510 Computer Organization and ArchitectureS-R Latch, from two NOR gates.S – Set – input to top NORR – Reset – input to bottom NORRace conditions when S=R=1 goes to S=R=0Indeterminate outcomePg 141TannenbaumCSIS 3510Dr. HogansonMemory ConstructionPg 142TannenbaumCSIS 3510Dr. HogansonMemory ConstructionSolve the S=R=1 problem Pg 143TannenbaumCSIS 3510Dr. HogansonMemory ConstructionAnother S-R FFEdge-triggered S-R Flip FlopCircuit (a) produces a momentary clock pulseLength of the pulse is determined by delay of the invertor before b changesShort clock pulse allows control of input timingPg 144-145TannenbaumCSIS 3510Dr. HogansonMemory ConstructionPackaging D Gates in Chips•This chip has 14 pins, including V and GND.•Two D FFs in a single package•Includes D, Q, not-Q, and Clock (CK)•Also Preset (PR) sets to 1 regardless of D•Also has Clear (CLR) which resets to zero•A simple integrated circuitPg 147TannenbaumCSIS 3510Dr. HogansonMemory ConstructionPackaging D gates•Larger scale of integration (almost 100 transistors)•Access to Q, D, on each chip•CK and CLR are “ganged” together•Stores a single byte of data (8 bits, one per D FF)Pg 147TannenbaumCSIS 3510Dr. HogansonMemory Construction4 X 3 Memory4 words of memory3 bits per wordDecoder selects word, based on A1 and A0 (two address lines) on the left of the diagramThree data lines in (on top)Three data lines out (on bottom)Common Chip-Select and RD linesOutput-Enable line (lower right) controls tri-states to the busPg 148TannenbaumCSIS 3510Dr. HogansonMemory ConstructionAlternative Memory OrganizationPg 150TannenbaumTwo ways to organize the same amount of memory (4M bits)Right diagram (4096K x 1) needs 22 address lines (4 M addresses)Address is read in two phases (11 bits each phase) – slower memoryNote: different numbers of pins needed for each designCSIS 3510Dr. HogansonMemory ConstructionMemory Design ProblemRam chips have 28 pinsNeed 1M addresses of 16 bitsAs usual, need V+, GND, R/W, Chip-SelectA) Determine the best organization. Explain/justify your answer and show all your work.B) Draw a schematic diagram of your solutionCSIS 3510Dr. HogansonMemory ConstructionAddr Data Mem Org Bits/ChipChips for WordWords for AddrTotal Chips23 1 223 X 1 8M X 1 8M 16 1 1622 2 222 X 2 4M X 2 8M 8 1 821 3 221 X 3 2M X 3 6M 6 1 620 4 220 X 4 1M X 4 4M 4 1 419 5 219 X 5 512K X 5 2.5M 4 2 818 6 218 X 6 256k X 6 1.5M 3 4 1217 7 217 X 7 128K X 7 896K 3 8 2416 8 216 X 8 64K X 8 512K 2 16 32The 1M X 4 organization minimizes chip count, with no unused bits on the chip. A single bank is required, so no decoder will be needed.CSIS 3510Dr. HogansonMemory