Introduction to Embedded Control System Design, EE138, Spring 2012 Page 1 of 5 San José State University College of Engineering/Electrical Engineering EE138, Introduction to Embedded Control System Design Section 01, Spring 2012 Instructor: Tri Dinh Office Location: Engineering E383 Telephone: 408-579-2820 Email: [email protected] Office Hours: Half-hour before classes or by appointment Class Code/Days/Time: 26763, MW 18:00 – 19:15 Classroom: Engineering E401 Labroom: Engineering E244 (Open Lab) Prerequisites: EE118, EE120 Course Description Embedded system design (ESD) challenge and metrics. Processor and IC technologies. Software and hardware architectures for ESD. Design flow and tools. The design of standard peripherals, microcontrollers, single-purpose and general purpose processors. Basic concepts of interfacing and communication protocols in ESD. The course will utilize Verilog HDL as design entry and FPGA as design platform. The topics include digital system design, embedded systems architecture, FPGA architecture, FPGA-base embedded processors, memory system design, FPGA-based Signal Interfacing, I/O components, and PCB design issues. Student Learning Objectives Upon successful completion of this course, students will be able to: 1. Describe in reasonable details architect of an embedded system. 2. To understand and be able to apply the digital design methodology. 3. To be able to use Verilog HDL to design, simulate, debug, test, and evaluate the operation and performance of an FPGA-based embedded system. 4. To understand and be able to design a memory system with all types of memory component.Introduction to Embedded Control System Design, EE138, Spring 2012 Page 2 of 5 5. To understand and be able to apply the theory and operation characteristics of serial and parallel communication interfaces, standard communication specifications and design techniques, the control of communication interfaces and related peripherals. 6. To understand and be able to design the I/Os of an embedded system. 7. To be able to design an embedded system and its interfaces. 8. To understand and be able to read, debug, and modify a schematic of an embedded system. 9. To be able to report your experiments, analysis, design, etc. in comprehensive formal writing and oral presentation formats, where the technical content, the appearance, the presentation, etc. are all considered to be important. 10. To be able to work in a group, to share experience and knowledge, to keep-up individual responsibility and to communicate professionally and effectively with the group members Required Texts/Readings Textbook Dubey, Rahul. “Introduction to Embedded System Design Using FPGAs”, 2009, ISBN 978-1-84882-015-9 Software Tools Xilinx ISE, Modelsim, ORCAD Referencess 1. Tammy Noergaard, “The Embedded Systems Architecture”, Elsevier. 2. J. Bhasker, “A Verilog HDL Primer”, Star Galaxy Press. 3. Data sheets and Application Notes. Classroom Protocol • Five laboratory exercises and a design projects will be assigned during the semester and are due by the due dates. All reports must be prepared neatly and professionally. The technical contents, format, completeness, and appearance of the report all contribute to the report's grade. Requests for rewriting the reports after they were graded are unacceptable. • Student names on the reports must be your official names. Nicknames must not be used for the reports and exams. • You are responsible to include all requested and necessary information in your reports. Reports must be condensed but completed, clear, firm, and prepared with care. Please keep in mind that reports will be graded for their technical contents, format, completeness, and appearance. Dropping and Adding Students are responsible for understanding the policies and procedures about add/drops, academic renewal, etc. Information on add/drops are available at http://info.sjsu.edu/web-Introduction to Embedded Control System Design, EE138, Spring 2012 Page 3 of 5 dbgen/narr/soc-fall/rec-298.html. Information about late drop is available at http://www.sjsu.edu/sac/advising/latedrops/policy/ . Students should be aware of the current deadlines and penalties for adding and dropping classes. Assignments and Grading Policy Where the weights of all assignments and examinations are: • Five Laboratory exercises : 50% • Midterm examination: 15% • Final Project : 15% • Final examination: 20% • Scores above average curve B to A • Average and below curve B- to F • Final project report must be submitted before the final exam date. • There will be one midterm exam and a comprehensive final exam. The date of the midterm exam will be determined. The final exam date is Monday, May 21, 2012, 17:15-19:30 • All exams will be CLOSED BOOK exams • Exams will cover the assigned reading materials, discussed materials in the lectures, and information from the lab exercises and the design projects. • There will be no make-up exams (in very special circumstances, written excuse and official proofs are required for making-up exam). • To pass the course, a student must to submit all labs, project, and take midterm and final exams. University Policies Academic integrity Students should know that the University’s Academic Integrity Policy is availabe at http://www.sa.sjsu.edu/download/judicial_affairs/Academic_Integrity_Policy_S07-2.pdf. Your own commitment to learning, as evidenced by your enrollment at San Jose State University and the University’s integrity policy, requires you to be honest in all your academic course work. Faculty members are required to report all infractions to the office of Student Conduct and Ethical Development. The website for Student Conduct and Ethical Development is available at http://www.sa.sjsu.edu/judicial_affairs/index.html. Instances of academic dishonesty will not be tolerated. Cheating on exams or plagiarism (presenting the work of another as your own, or the use of another person’s ideas without giving proper credit) will result in a failing grade and sanctions by the University. For this class, all assignments are to be completed by the individual student unless otherwise specified. If you would like to include in your assignment any material you have submitted, or plan to submit for another class,