hspice book hspice ch21 1 Thu Jul 23 19 10 43 1998 Chapter 20 Signal Integrity The performance of an IC design is no longer limited to how many million transistors a vendor fits on a single chip With tighter packaging space and increasing clock frequencies packaging and system level performance issues such as crosstalk and transmission lines are becoming increasingly significant At the same time with the popularity of multichip packages and increased I O counts package design itself is becoming more and more like chip design This chapter describes how to maintain signal integrity for you design and covers the following topics Preparing for Simulation Optimizing TDR Packaging Simulating Circuits with Signetics Drivers Simulating Circuits with Xilinx FPGAs PCI Modeling Using Star Hspice Analyzing Board Signal Integrity Star Hspice Manual Release 1998 2 20 1 hspice book hspice ch21 2 Thu Jul 23 19 10 43 1998 Preparing for Simulation Signal Integrity Preparing for Simulation To simulate a PC board or backplane with Star Hspice you must consider models for A driver cell including the parasitic pin capacitances and package lead inductances Transmission lines A receiver cell with its parasitic pin capacitances and package lead inductances Terminations or other electrical elements on the line It is important to model the transmission line as closely as possible that is to include all electrical elements exactly as they are laid out on the backplane or printed circuit board to maintain the integrity of the simulation With readily available I O drivers from ASIC vendors and Star Hspice s advanced lossy transmission lines you can simulate the electrical behavior of the board interconnect bus or backplane to analyze the transmission line behavior under various conditions Simulation is possible because the critical models and simulation technology exist Many manufacturers of high peed components use Star Hspice already The complexity can be hidden from the systems level The necessary electrical characteristics are preserved with full transistor level library circuits Star Hspice has been enhanced for systems simulation with Systems level behavior such as local component temperature and independent models to allow accurate prediction of electrical behavior Automatic inclusion of library components via the SEARCH option Lossy transmission line models that Support common mode simulation Include ground plane reactance 20 2 Star Hspice Manual Release 1998 2 hspice book hspice ch21 3 Thu Jul 23 19 10 43 1998 Signal Integrity Preparing for Simulation Include resistive loss of conductor and ground plane Allow multiple signal conductors Require minimum CPU computation time The following vendor models are currently available in Star Hspice Signetics FAST Library Xilinx 3000 4000 Series FPGA Intel s Peripheral Component Interconnect PCI high speed local bus Signal Integrity Problems Some signal integrity problems that can cause failures in high speed designs are listed in Table 20 1 Table 20 1 High Speed Design Problems and Solutions Signal Integrity Problem Causes Solution Noise delta I current Multiple simultaneously switching drivers high speed devices create larger delta I Adjust or evaluate location size and value of decoupling capacitors Noise coupled crosstalk Closely spaced parallel traces Establish parallel line length design rules Noise reflective Impedance mismatch Reduce the number of connectors and select proper impedance connectors Delay path length Poor placement and routing too many or too few layers chip pitch Choose MCM or other high density packaging technology Propagation speed Dielectric medium Choose dielectric with lowest dielectric constant Delay rise time degradation Resistive loss and impedance mismatch Adjust width thickness and length of line Star Hspice Manual Release 1998 2 20 3 hspice book hspice ch21 4 Thu Jul 23 19 10 43 1998 Preparing for Simulation Signal Integrity Analog Side of Digital Logic Circuit simulation of a digital system only becomes necessary when the analog characteristics of the digital signals become electrically important Is the digital circuit a new design or simply a fast version of the old design Many new digital products are really faster versions of existing designs The transition from a 100 MHz to a 150 MHz Pentium PC may not require extensive logic simulations However the integrity of the digital quality of the signals may require very careful circuit analysis The source of a signal integrity problem is the digital output driver A high speed digital output driver can only drive a few inches before the noise and delay due to the wiring become a problem To speed up circuit simulation and modeling you can create analog behavioral models that mimic the full analog characteristics at a fraction of the traditional evaluation time The simulation of the output buffer in Figure 20 1 demonstrates the analog behavior of a digital gate simulated in the Star Hspice circuit simulator 20 4 Star Hspice Manual Release 1998 2 hspice book hspice ch21 5 Thu Jul 23 19 10 43 1998 Signal Integrity Preparing for Simulation vdd D OUT Ground Current VDD Current Ground noise Figure 20 1 Simulation of Output Buffer with 2 ns Delay and 1 8 ns Rise and Fall Times The roadblocks to successful high speed digital designs are noise and signal delays Digital noise can come from several sources The fundamental digital noise sources are Line termination noise Ground bounce noise Coupled line noise Line termination noise is the additional voltage that is reflected from the load back to the driver because of impedance mismatch Digital output buffers are not designed to have accurately controlled output impedance and most buffers have different rising and falling edge impedances Star Hspice Manual Release 1998 2 20 5 hspice book hspice ch21 6 Thu Jul 23 19 10 43 1998 Preparing for Simulation Signal Integrity Ground bounce noise is generated where leadframes or other circuit wires cannot be formed into transmission lines The resulting inductance creates an induced voltage in the ground circuit the supply circuit and the output driver circuit The ground bounce noise lowers the noise margins for the rest of the system Coupled line noise is the noise induced from lines that are physically adjacent This noise is generally most severe for data lines that are next to clock lines Circuit delays become critical as timing requirements become tighter The key circuit delays are Gate delays Line