CS311 Lecture: Sequential CircuitsLast revised 8/15/2007Objectives:1. To introduce asynchronous and synchronous flip-flops (latches and pulse-triggered, plus asynchronous preset/clear)2. To introduce SR, D, and JK configurations3. To show how to implement a finite state machine using flip-flops and combinatorial networks Materials: 1. Circuit Sandbox and demonstration circuits Asynchronous Flip Flop, Latch, Race, Master-Slave, Master-Slave with Preset+Clear, D Flip-Flop, JK Flip-Flop, Traffic Light Controller, Traffic Light Controller with Walk Flip-Flop, Divide by Three CounterI. Introduction A. Thus far, we have been discussing COMBINATORIAL logic circuits. These have the property that the output at any time is a boolean function of the inputs (with some propagation delay when inputs change).B. Complete computer systems also require circuits that have MEMORY - that is, circuits whose output can be a function of the input AT SOME TIME in the past. Such circuits are used for:1. Internal memory: registers, main memory2. Control circuits that cycle the system through the series of steps comprising the algorithm for a given task. (The system must keep track of its state - what step it is currently on - in order to know what to do next.II. Flip FlopsA. It turns out to be quite easy to use our combinatorial building blocks to construct a circuit that has memory - i.e. whose output is a function of past as well as present inputs.The following is an example of such a circuit, called a flip-flop:1Suppose we were to try to develop a “truth table” for this circuit, where we treat S' and R' as inputs and Q and Q' as outputs.ASK CLASS FOR OUTPUTS FOR EACH ROWS' R' Q Q'0 0 1 10 1 1 01 0 0 11 1 ??? - depends on prior valuesObserve:1. When both S' and R' are high (1), there are two stable states:a) If Q is low, then Q' is high (since the lower gate now has one low input and one high.) This state is stable, since the upper NAND gate now has two high inputs, making its output low.b) If Q is high, then Q' is low (since the lower gate has both inputs high). This state is also stable, since the upper NAND gate has one low input and one high input, making its output high.c) When the circuit is first turned on, the flip flop will go into one of these two states non-deterministically. (Actually, slight physical differences in the transistors in the two gates will usually serve to decide the state.d) The two stable states are conventionally called 0 and 1 or low and high, corresponding to the value of Q.e) Note the relationship of Q and Q' when in a stable state: they are inverses (hence the choice of labels Q and Q')22. Effect of momentarily setting either S' or R' to low (0).a) If the flip-flop is in the stable state with Q low then setting R' low has no effect. However, setting S' low flips the state to the state with Q high, where the circuit will remain even after S returns to high.The input is labelled R' because it is ACTIVE LOW, and its effect is to reset the flip-flop (put it in the 0 state). (Note: sometimes documentation just calls this input R, rather than R-bar).b) If the flip-flop is in the stable state with Q high then setting S' low has no effect. However, setting R' low flips the state to the state with Q low, where the circuit will remain even after R returns to high.The input is labelled S' because it is ACTIVE LOW, and its effect is to set the flip-flop (put it in the 1 state). (Note: sometimes documentation just calls this input S, rather than S-bar).3. Effect of momentarily setting both S' and R' low:a) If both S' and R' are low, then both Q and Q' go high, since each gate now has one low input. This, of course, violates the intention of the labels that Q and Q' should be opposites.b) If both S' and R' are restored to the high state at the exact same time, the state of the flip flop is intedeterminate: it will settle into one of the two stable states. Which one, however, cannot be predicted.c) For these reasons, having both R' and S' low at the same time is regarded as an illegal input pattern for this kind of flip-flop.4. DEMONSTRATE (File Asynchronous SR flip-flop)5. This is variously called an RS flip-flop or an SR flip-flop, and has its own special symbol:6. One can build a similar circuit from NOR gates - but we won't pursue this here.3B. One important characteristic of the flip flop we have been considering is that it is ASYNCHRONOUS - that is, the output changes almost instantaneously when the input changes. (There is a slight delay due to internal switching times of the gate.) 1. This can pose a problem if one builds a register, in which several flip-flops are used to represent a multi-bit value (e.g. 32 flip-flops could bu used to represent a 32 bit number). In this case, one would like all the flip-flops to change state at the same time - which we call SYNCHRONOUS behavior. (The state changes are synchronized)2. One can easily build a clocked variant of this kind of flip flop, in which the state changes only when a special clock pulse is received. This makes it possible to synchronize state changes. The following has the property that state changes occur only when the clock input is high:a) When the clock input is low (0), the outputs of both gates are necessarily high (1) - which ensures that the flip-flop will remain in whatever state it is in, regardless of the external inputs.b) When the clock input is high (1), and both S and R are low (0), the output of both gates is again high, which leaves the state of the flip-flop unchanged.c) When the clock input is high, a high on either S or R becomes a low at the output of the corresponding gate, which in turn sets or clears the flip-flop. d) We disallow having both S and R high at the same time)e) DEMONSTRATE (file Latch)f) This kind of flip-flop is called a level-triggered flip-flop or a LATCH (it latches onto the input when the clock is high), and has the following symbol:4C. However, even this device is not adequate for all situations. 1. Consider what would be inolved in building a flip-flop whose output feeds back to its input. Such a situation might arise, for example, if one were trying to build a COUNTER - a device that counts the number of clock pulses it receives. For example, the following is a one-bit counter - it is intended to go through the sequence of states 0, 1, 0 , 1, 0, 1 ...This circuit will not work as intended. Why?ASKThere is a race condition in the circuit - if