CS311 Lecture: Basic Von Neumann Architecture; Introduction to the MIPS Architecture and Assembly LanguageLast revised 9/2/2009Objectives:1. To introduce the MIPS architectur2. To introduce MIPS R-Type, immediate, and load-store instructions Materials: 1. MIPS ISA Handout (will have been distributed before class)2. Connection to MIPS to demo gccI. Introduction A. For the next few weeks, we will be studying the Machine Language level of system description. At this level, a computer system can be iewed as a memory, a set of registers, and a set of instructions for manipulating the information in the memory and registers.1. Programs written at a higher level of system description (e.g. in a language such as C) are translated into primitive operations at this level.2. This level is, in turn, implemented directly by hardware - i.e. the registers are arrays of flip-flops, addition is performed by full adders, etc.3. The architectural description of a machine at this level is often refered to an Instruction Set Architecture (ISA).B. For this portion of the course, we will be focussing on a particular instruction set architecture (ISA) known as MIPS.1. It is not the goal of these lectures that you should become proficient MIPS assembly or machine language programmers.2. Rather, we want to use MIPS as an example of a typical instruction set architecture.a) The MIPS architecture belongs to the general category of Reduced Instruction Set Computer (RISC) architectures. 1(1) As such, it is easier to learn than a Complex Instruction Set Computer (CISC) architecture such as the IA32 architecture used by the Pentium. (2) All brand new instruction set architectures defined since 1985 have been RISC. (The first RISC architectures were defined in the early 1980's.)(a) e.g. Intel's 64-bit architecture (IA64) that was slated to replace the current IA32 architecture is a RISC architecture. (The reasons for this have to do with RISC architectures facilitating producing higher-performance systems - a subject we will discuss later).(b) However, Intel decided to extend the current IA32 (Pentium) architecture to 64 bits instead, for reasons of backward compatibility(3) The current practice is to implement CISC architectures on top of a RISC core (there is a RISC inside the CISC) - for example, this is how newer Pentiums are actually being implemented.b) When we get to the actual details of implementing a CPU (computer organization), the implementation of a RISC architecture like MIPS is more comprehensible - and, indeed, we will discuss the implementation of the MIPS architecture in later lectures.3. It is also the case that once you have become familiar with one instruction set architecture, it is much easier to learn another. (Once you learn to drive a Ford, driving a Chevy is easy.)C. A bit of history1. The MIPS architecture grows out of an early 1980's research project at Stanford University. 2. In 1984, MIPS computer corporation was founded to commercialize this research. However, CPU chips based on the MIPS architecture have been produced by a number of different companies, including LSI Logic, Toshiba, Philips, NEC, IDT, and NKK.3. The MIPS architecture has passed through a series of evolutions, known as MIPS I, MIPS II, MIPS III, and MIPS IV.2a) Each successive ISA is a superset of the preceeding one - so anything found in MIPS I is also found in MIPS II, III, and IV, etc.b) The MIPS I and II ISA's were 32 bit architectures. MIPS III added 64 bit capabilities - but with the core 32 bit architecture as a subset.c) We will confine our coverage to the core MIPS I architecture.4. Note that the MIPS architecture itself is older than you are! That may seem surprising, given the rapid progress in the field of CPU performance. However, the changes have mostly come at the implementation level, not the architectural level.(Compare: Today's cars are much safer, longer lasting, and environmentally friendly than those of decades ago - however, the basic architecture of gasoline engine, four wheels, a steering wheel, gas, brake and (optionally) clutch pedals has remained unchanged for decades.)D. Note that we are going to study the MIPS ARCHITECTURE. As is true of most successful architectures, There have been many this architecture - e.g. 1. R2000 - the original implementation, and the one whose implementation we will discuss later in the course2. R3000, R30513. MIPS R6000 (implemented MIPS II ISA) *4. MIPS R4000, Vr4300, R4400, R4600 (implemented MIPS III ISA)* The R6000 preceeded the R4000 because the R4000 took longer than planned to develop, but was quickly superseded by the R40005. MIPS R5000 (implemented MIPS IV ISA)6. MIPS R100007. Various specialized implementations used in embedded systems (printers, routers, game consoles)E. Note: the system we will use in lab uses the R5000 implementation.3II. Basic MIPS-I ArchitectureA. Although MIPS implementations differ in internal organization, they can all be regarded as having the same basic architecture.(Go over diagram in handout. Note: IO Devices will be discussed later in the course and vary widely from installation to installation.)B. Discuss handout material on CPU registers1. The CPU has 35 user-visible REGISTERS (plus several typically used only by the operating system). Each register holds one word (32 bits).2. Registers can be thought of as a very special kind of memory cell.a) Registers are part of the CPU, mot the memory system.b) A register is referred to by name (e.g. $31, pc) instead of by address.c) Information in a register can be accessed in much less than one clock cycle (e.g. much less than a nanoseconds on a 1GHz + machines). In contrast, information in memory requires 10's of ns to access.3. Discussa) 32 general registersb) pcc) hi and lod) Note that - in contrast to the VonNeumann machine, there is no IR. That's because MIPS uses a pipelined implementation in which several instructions are at different stages of processing at any one time. There are several "IR's" that are part of the pipeline registers, as we shall see later.C. Discuss Handout material on Memory1. The amount of physical memory installed will vary from system to system Special hardware and software gives the user the appearance of a much larger VIRTUAL MEMORY by using disk as an extension of main memory to hold regions not currently being used.42. Addresses whose leftmost bit is 1 (0x80000000 to 0xffffffff) are handled in special ways by