CS 636 Internetworking Ramana Kompella ROUTER ALGORITHMICS Lecture 12: Switching (CIOQ switches, Parallel packet switches) Slides courtesy of Balaji Prabhakar and Sundar Iyer 1 A CIOQ switch consists of ◦ An internally non-blocking fabric with speedup S > 1 ◦ Input and output buffers ◦ A scheduler to determine matchings  Logically, ◦ Each time slot consists of two phases ◦ Arrivals to switch occur at most once per slot ◦ One cell transferred in each phase. 2 CS 636 Internetworking Enter speedup (S) ◦ S = 1 in an i/q switch (mem. bwdth. = 2) ◦ S = N (mem. bwdth. = N+1)  Suppose we consider switches with fabric speedup of S, 1 < S N ◦ Such switches will require buffers both at the input and the output (why?)  Such switches could help if... ◦ With very small values of S ◦ Now let us look at a bit of background research into speedup... 3 CS 636 Internetworking Emulation: Apply the same inputs, cell-by-cell to both switches and order of cells should match. 4 CS 636 Internetworking Urgency = departure time – current time  Algorithm : most urgent cell first (MUCF)  In each phase, ◦ Outputs get most urgent cells first from inputs ◦ Inputs grant to outputs whose cell is most urgent  Ties are broken based on port number ◦ Loser outputs try to obtain next urgent cell ◦ No more matchings possible, cells are transferred 5 CS 636 Internetworking Cell not forwarded from input to output for two reasons ◦ Input contention: input sends a more urgent cell ◦ Output contention: output receives a more urgent cell 6 CS 636 Internetworking Output thread: The output thread of a cell c for output O is the ordered set of cells in the input side more urgent than c for output O.  Input thread: The input thread of cell c at input I is the ordered set of cells at input I that are more urgent than c 7 CS 636 Internetworking A combined input- and output-queued switch with a speedup of 4 operating under the MUCF algorithm exactly matches cells with a FIFO output-queued switch. Here the arrival patterns and switch size are arbitrary. ◦ note that the output thread of a cell c with urgency U is no more than U cells long ◦ the theorem is proved by showing that when S ≥ 4, the same is true of input threads  Claim : At any time, and for any cell c, max {IT,OT}≤U (if S ≥ 4 and MUCF is used to schedule cells. 8 CS 636 Internetworking9 CS 636 Internetworking10 CS 636 Internetworking MUCFA does not work with speedup 3 ◦ Counter example given by S.T. Chuang  IT ≤ U (and OT ≤ U always)  Therefore IT + OT ≤ 2U for all times if S ≥ 4  Question: Can we show IT + OT ≤ 2U if S ≥ 2  Answer: Yes 11 CS 636 Internetworking Example: WFQ, strict priority  Key concept: expected departure time ◦ EDT(t) = departure time of c if no other cells arrived for its output in the future  We can show that max {IT(t), OT(t)} ≤ EDT (t) for all cells at time t if S ≥ 4. 12 CS 636 Internetworking13 CS 636 InternetworkingCS 636 Internetworking 14  All packet switches (e.g. Internet routers, Ethernet switch) require packet buffers for periods of congestion.  Size: For TCP to work well, “rule of thumb” says that buffers need to hold one RTT (about 0.25s) of data.  Speed: Clearly, the buffer needs to store (retrieve) packets as fast as they arrive (depart). Memory Linerate, R Memory Linerate, R Linerate, R Linerate, R Memory 1 N 1 NCS 636 Internetworking 15 Buffer Memory Write Rate, R One 40B packet every 8ns Read Rate, R One 40B packet every 8ns 10Gbits Buffer Manager UnpredictableScheduler RequestsCS 636 Internetworking 16  Use SRAM? + Fast enough random access time, but - Too low density to store 10Gbits of data.  Use DRAM? + High density means we can store data, but - Can’t meet random access time.CS 636 Internetworking 17 Buffer Memory Write Rate, R One 40B packet every 8ns Read Rate, R One 40B packet every 8ns Buffer Manager Buffer Memory Buffer Memory Buffer Memory Buffer Memory Buffer Memory Buffer Memory Buffer Memory Read/write 320B every 32ns 40-79 Bytes: 0-39 … … … … … 280-319 320B 320BCS 636 Internetworking 18 Write Rate, R One 40B packet every 8ns Read Rate, R One 40B packet every 8ns Buffer Manager 40-79 Bytes: 0-39 … … … … … 280-319 320B Buffer Memory 320B 40B 320B 320B 40B 40B 40B 40B 40B 40B 40B 40B 40B 320B 320B 320B 320B 320B 320B 320B 320B 320B 320BCS 636 Internetworking 19 Write Rate, R One 40B packet every 8ns Read Rate, R One 40B packet every 8ns Buffer Manager 40-79 Bytes: 0-39 … … … … … 280-319 320B Buffer Memory 320B ?B 320B 320B ?B 320B 320B 320B 320B 320B 320B 320B 320B 320B 320B Variable Length PacketsCS 636 Internetworking 20 1. A 320B block will contain packets for different queues, which can’t be written to, or read from the same location. 2. If instead a different address is used for each memory, and packets in the 320B block are written to different locations, how do we know the memory will be available for reading when we need to retrieve the packet?CS 636 Internetworking 21 40-79 Bytes: 0-39 … … … … … 280-319 320B 320B 320B 320B 320B 320B 320B 320B 320B 320B 320B 320B 1 2 Q e.g.  Q might be 1k – 64k Write Rate, R One 40B packet every 8ns Read Rate, R One 40B packet every 8ns Buffer Manager 320B 320B ?B 320B 320B ?B How can we write multiple variable-length packets into different queues?CS 636 Internetworking 22 Arriving Packets R Unpredictable Scheduler Requests Departing Packets R 1 2 1 Q 2 1 2 3 4 3 4 5 1 2 3 4 5 6 Small head SRAM cache for FIFO heads SRAM Large DRAM memory holds the body of FIFOs 5 7 6 8 10 9 7 9 8 10 11 12 14 13 15 50 52 51 53 54 86 88 87 89 91 90 82 84 83 85 86 92 94 93 95 6 8 7 9 11 10 1 Q 2 Writing b bytes Reading b bytes cache for FIFO tails 55 56 96 97 87 88 57 58 59 60 89 90 91 1 Q 2 Small tail SRAM DRAMCS 636 Internetworking 23 1. What is the minimum SRAM needed to guarantee that a byte is always available in SRAM when requested? 2. What algorithm should we use to manage the replenishment of the SRAM “cache” memory?CS 636 Internetworking 24 t = 1 Bytes t = 3 Bytes t = 4 Bytes t = 5 Bytes t = 7 Bytes t = 2 Bytes t = 6 Bytes t = 0 Bytes Replenish