CS 636 InternetworkingRamana KompellaLecture 4: Implementation Models [continued]CS 636 Internetworking 1Some slides courtesy of Nick McKeownCS 636 InternetworkingThis Lecture Networking (protocols) Hardware Device architecture Operating systems2Architecture Models Optimizing network performance requires optimizing all data paths ◦ Through the internals of source node, sink node and routers End node architectures optimized for general computation. Router architectures for Internet communication.CS 636 Internetworking 3End Node Architecture Main memory (1GB, 50-80nsec, L2 cache, on chip SRAM registers) Direct mapped caches ◦ Cache lines, spatial locality, page mode Memory mapped I/O, DMA, I/O bus versus processor bus. CS 636 Internetworking 4Alternative endnode architecture Packets from network  Mem2 Processor Reads  Mem1 Switch can alternate the accesses E.g., infiniband as a replacement for PCICS 636 Internetworking 56What a Router Looks LikeCisco GSR 12416 Juniper M1606ft19”2ftCapacity: 160Gb/sPower: 4.2kW3ft2.5ft19”Capacity: 80Gb/sPower: 2.6kWRouter Architectures Major tasks:◦ Lookup◦ Classification◦ Switching◦ Queuing Less time-critical◦ Header verification◦ Checksum◦ Route computationCS 636 Internetworking 78Generic Router ArchitectureLookupIP AddressUpdateHeaderHeader ProcessingData Hdr Data Hdr1M prefixesOff-chip DRAMAddressTableIP Address Next HopQueuePacketBufferMemory1M packetsOff-chip DRAMSlide courtesy of Nick McKeown9Generic Router ArchitectureLookupIP AddressUpdateHeaderHeader ProcessingAddressTableLookupIP AddressUpdateHeaderHeader ProcessingAddressTableLookupIP AddressUpdateHeaderHeader ProcessingAddressTableData HdrData HdrData HdrBufferManagerBufferMemoryBufferManagerBufferMemoryBufferManagerBufferMemoryData HdrData HdrData HdrNetwork Processors General purposes processors optimized for network traffic◦ Motivated by unpredictable router tasks Often just multiple processors that work on different packets at the same time◦ Intel IXP has 6 processors with 5.6ns clock Use multithreading to quickly switch contexts◦ IXP has 4 contexts Special purpose instructions for address lookup and other functionsCS 636 Internetworking 1011Why NPUs seem like a good idea What makes a CPU appealing for a PC◦ Flexibility: Supports many applications◦ Time to market: Allows quick introduction of new applications◦ Future proof: Supports as-yet unthought of applications No-one would consider using fixed function ASICs for a PC12Why NPUs seem like a good idea What makes a NPU appealing◦ Time to market: Saves 18months building an ASIC. Code re-use.◦ Flexibility: Protocols and standards change.◦ Future proof: New protocols emerge.◦ Less risk: Bugs more easily fixed in s/w. Surely no-one would consider using fixed function ASICs for new networking equipment?13Network ProcessorsLoad-balancingcachecachecachecachecacheOff chip MemoryDispatchCPUCPUCPUCPUCPUCPUDedicatedHW support, e.g. lookupsDedicatedHW support, e.g. lookupsDedicatedHW support, e.g. lookupsDedicatedHW support, e.g. lookupsIncoming packets dispatched to:1. Idle processor, or2. Processor dedicated to packets in this flow(to prevent mis-sequencing), or3. Special-purpose processor for flow,e.g. security, transcoding, application-levelprocessing.14Network ProcessorsPipeliningcacheOff chip MemoryCPUcacheCPUcacheCPUcacheCPUDedicatedHW support, e.g. lookupsDedicatedHW support, e.g. lookupsDedicatedHW support, e.g. lookupsDedicatedHW support, e.g. lookupsProcessing broken down into (hopefully balanced) steps,Each processor performs one step of processing.CS 636 InternetworkingModels Networking (protocols) Hardware Device architecture Operating systems15Operating System Routers usually have a lightweight OS◦ Different from traditional Oses End-node performance dependent on OS Abstractions◦ Uninterrupted Computation: No Interrupts◦ Infinite Memory: just an illusion.◦ Simple I/O : Avoid dealing directly with devices (simple writes/reads)CS 636 Internetworking 16Uninterrupted communication Underlying mechanisms◦ Context switching◦ Scheduling◦ Protection Flavors of “process” – increasing complexity◦ Interrupt handlers, threads, processesCS 636 Internetworking 17Receiver livelock in BSD Keep processing packets only to discard because apps never run. Latency depends on process◦ Interrupts (10us), context switch (10-100us)CS 636 Internetworking 18Infinite memory Via virtual memory◦ Page mapping (avoids finding contiguous locations)◦ Demand paging (use more space than memory) Slow DRAM lookup avoided with fast TLB Protection by allowing only OS to modify page tablesCS 636 Internetworking 19Simple I/O using system calls For abstraction alone, I/O could be libraries For security, I/O handled by device drivers System calls, trap to kernel protection levels More expensive function call, because of privilege escalationCS 636 Internetworking 20Next class… Implementation principles Read chapter 3 (and 4 if you are interested)CS 636 Internetworking