1 M68HCS12 Parallel I/O (Excerpt from a completely new chapter on HCS12 parallel I/O). The complete chapter details are at http://www.coe.montana.edu/ee/courses/ee/ee371/pdffiles_parallel_io.pdf Port P PORT PInterrupt LogicPWMPWM0PWM1PWM2PWM3PWM4PWM5PP0PP1PP2PP3PP4PP5PP6PP7To Port TMUX Figure 1 Port P (Only PP5 available in the Lab) Port P is an 8-bit, general-purpose I/O port. Alternatively, up to six pulse-width modulated waves can be output. In some versions of the microcontroller, such as the 9S12C32 where the Port P pins are not available at the chip, five of the six PWM outputs can be routed to Port T. The Module Routing Register – MODRR, as discussed below is used to do this. PTP – Base + $0258 – Port P I/O Register Bit 7 6 5 4 3 2 1 0 Read: Write: PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 Reset: 0 0 0 0 0 0 0 0 PWM - - PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 See Also: Topic Register Chapter Port P Input Register Data Direction Register Reduced Drive Control Pull-Up or Pull-Down Enable Polarity Select Register Port P Interrupt Enable Port P Interrupt Flag Pulse-Width Modulation PTIP (Base + $0259) DDRP (Base + $025A) RDRP (Base + $025B) PERP (Base + $025C) PPSP (Base + $025D) PIEP (Base + $025E) PIFP (Base + $025F) Data Direction Registers Each bit in the bidirectional data registers may be programmed to be either input or output. When the CPU is reset, all registers are placed in the input mode, and you must set bits in a Data Direction Register – DDR to change input bits to be outputs. Each DDR has the format shown2 below where x is A, B, AD, E, J, M, P, S or T; the addresses for each are given in shows how to initialize the most significant nibble in Port P for output. If a port has a mixture of input and output bits, writing to the port affects only those bits that are outputs. Reading the port returns the values on the input bits as well as the last values output to the output bits. DDRx – Base + $(Table 1) – Port x Data Direction Register Bit 7 6 5 4 3 2 1 0 Read: Write: DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0 Reset: 0 0 0 0 0 0 0 0 Default: Input Input Input Input Input Input Input Input = reserved, unimplemented or cannot be written to. Read: Anytime. Write: Anytime DDRx7:DDRx0 Data Direction Control Bits. 0 = Associated pin is high-impedance input (default). 1 = Associated pin is an output. Data direction register bits determine the direction of the corresponding data register. The direction can be set individually for each bit in the port. Table 1 Data Direction Register Addresses Data Direction Register Address Base + DDRA DDRB DDRAD DDRE1 DDRJ DDRM DDRP DDRS DDRT $0002 $0003 $0272 $0009 $026A $0252 $025A $024A $0242 Example 1 Initializing the Data Direction Register Metrowerks HC12-Assembler (c) COPYRIGHT METROWERKS 1987-2003 Rel.Loc Obj. code Source line ---------- --------- ----------- 1 ; Set the register BASE address 2 0000 0000 BASE: EQU $0000 3 0000 0258 PTP: EQU BASE+$0258; Port P I/O 4 0000 025A DDRP: EQU BASE+$025A; DDR Port P 5 ; Define bits to be output and input 6 ; 1 = output, 0 = input 7 0000 00F0 OBITS: EQU %11110000 1 You cannot configure bits-0 and -1 in Port E to be output because they are associated with interrupt inputs.3 8 ; . . . 9 ; Set direction register for Port P 10000000 1C02 5AF0 bset DDRP,OBITS 11 ; . . . 12 ; Output data to bits 7 - 4 13000004 86B0 ldaa #%10110000 14000006 7A02 58 staa PTP 15 ; Read data on bits 3 - 0 16000009 B602 58 ldaa PTP Example 2 Initializing the Data Direction Register with C /***************************************** * Define bits to be output and input * 1 = output, 0 = input ****************************************/ #define OBITS 0xf0 /* 240 */ void main(void) { /* Set direction register for Port P */ DDRP = OBITS; /* . . . */ /* Output data to bits 7 - 4 */ PTP = 0xB0; /* . . . */ /* Or here is another way */ /* These compile to bit set and bit clr instructions */ /* Set direction register for Port P */ DDRP_DDRP7 = 1; DDRP_DDRP6 = 1; DDRP_DDRP5 = 1; DDRP_DDRP4 = 0; /* . . . */ /* Output data to bits 7 - 4 */ PTP_PTP7 = 1; PTP_PTP6 = 0; PTP_PTP5 = 1; PTP_PTP4 = 1; } I/O Port Bit Electronics Reduced Drive Control Drive refers to the capability of the output circuitry to source current to whatever is connected to the pin. High drive current is an advantage when the output must drive a capacitive load. High drive current results in higher speed switching between logic levels. Unfortunately, high drive current means higher power consumption and the increased likelihood of radio frequency interference (RFI). The RDRx, Port x Reduced Drive register allows you to reduce the drive level4 to reduce power consumption and RFI emissions for the registers in the Port Integration Module as shown in Table 2. If any of the port bits are used for an input, the reduced drive control bit is ignored. RDRx – Base + $(Table 2) – Port x Reduced Drive Register Bit 7 6 5 4 3 2 1 0 Read: Write: RDRx7 RDRx6 RDRx5 RDRx4 RDRx3 RDRx2 RDRx1 RDRx0 Reset: 0 0 0 0 0 0 0 0 RDRAD: Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive RDRJ: Full Drive Full Drive RDRM: Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive RDRP: Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive RDRS: Full Drive Full Drive Full Drive Full Drive RDRT: Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive = reserved, unimplemented or cannot be written to. Read: Anytime. Write: Anytime RDRx7:RDRx0 Reduced Drive for Ports 0 = Full drive strength at output. 1 = Associated pin drives at about 1/3 the full drive output. Table 2 Reduced Drive Enable Registers Pull Device Enable Register Address Base + RDRAD RDRJ RDRM RDRP RDRS RDRT $0273 $026B $0253 $025B $024B $0243 Pull-up or Pull-down Control It is a good electronic design practice to tie unused input pins to either a high or low logic level. In CMOS devices this