Chapter 14 – M68HCS12 Serial I/O 14-16 Example 14-5 SCI Put String Metrowerks HC12-Assembler (c) COPYRIGHT METROWERKS 1987-2003 Rel.Loc Obj. code Source line ---------- --------- ----------- 1 ;*************************************** 2 ; MC68HCS12 SCI I/O Example 3 ; Output null terminated string 4 ; Assembler routines: 5 ; put_str, putstr 6 ; C Routines 7 ; int putstr( char *); 8 ;*************************************** 9 ; Put null terminated string to sci 10 ; Inputs: D = starting address of string 11 ; Outputs: D = number of characters printed 12 ; Reg Mod: D, CCR 13 ;*************************************** 14 ; SCI port definitions 15 INCLUDE "sci.inc" 16 XDEF put_str, putstr 17 XREF putchar 18 ;*************************************** 19 put_str: 20 putstr: 21000000 34 pshx 22000001 35 pshy 23000002 B745 tfr d,x ; Initialize pointer to string 24 ; Use the Y register as counter of chars printed 25000004 CD00 00 ldy #0 ; Initialize counter 26 ; WHILE character to print is not a null 27 while_do: 28000007 E600 ldab 0,x 29000009 2707 beq done 30 ; DO 31 ; Print the character 3200000B 16xx xx jsr putchar 33 ; Increment the counter and pointer 3400000E 02 iny 3500000F 08 inx 36000010 20F5 bra while_do 37 done: 38000012 31 puly 39000013 30 pulx 40000014 3D rts 41 ;*************************************** 14.3 Synchronous Serial Peripheral Interface (SPI) The SPI is designed to send high-speed serial data to peripherals and other SPI equipped MCUs and digital signal processors.Chapter 14 – M68HCS12 Serial I/O 14-17 Interprocessor Serial Communications Figure 14-3 shows a typical application of the SPI. Two M68HCS12s are connected in a master/slave arrangement. The 8-bit shift registers in the master and slave make a circular 16-bit register. When data are to be transmitted from the master to the slave, a clock signal, SCK (Port M, bit-4), is generated by the master device to synchronize the transfer of each bit. Data are transferred out of each shift register simultaneously so that the master receives what was in the slave. The transmitted data are single buffered; this means that the program must wait until the last transmitted data bit is shifted out before writing new data to the register. A flag, SPIF - SPI Transfer Complete Flag, is available for polling or interrupts. Received data, on the other hand, are buffered and so the program has one character time to read the data before the next data overwrites it. The slave select signal, SS*, must be low to select a M68HCS12 as a slave and high for the master. Shift RegisterBuffer RegisterShift RegisterBuffer RegisterM68HCS12 MASTERM68HCS12 SLAVEMOSIMISOShift ClockSlave Select* Slave Select*SCKVDD Figure 14-3 Master/slave serial peripheral interface. SPI Data Register The SPI Data Register, SPIDR, is similar to the SCI Data Register in that two registers occupy one memory location, $00DD. Data to be transmitted serially are written to this register and serial data received are read from it. SPIDR – Base + $00DD – SPI Data Register Bit 7 6 5 4 3 2 1 0 Read: Write: Bit 7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 Read: Anytime; normally only after SPIF is set. Write: Anytime. The SPI is a synchronous serial interface because the master provides a clock to shift data in and out.Chapter 14 – M68HCS12 Serial I/O 14-18 SPI Initialization The SPI is initialized by the SPI Control Registers SPICR1 and SPICR2. SPICR1 – Base + $00D8 – SPI Control Register 1 Bit 7 6 5 4 3 2 1 0 Read: Write: SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE Reset: 0 0 0 0 0 1 0 0 Read: Anytime. Write: Anytime. SPIE SPI Interrupt Enable 0 = SPI interrupts are disabled (default). 1 = Interrupts are enabled. See SPI Status Register and SPI Interrupts. SPE SPI System Enable 0 = SPI system is in a low-power, disabled state (default). 1 = SPI enabled and Port M pins dedicated to SPI functions. SPTIE SPI Transmit Interrupt Enable 0 = SPTEF interrupt request disabled (default). 1 = SPTEF interrupt enabled. See SPI Status Register and Interrupts. MSTR SPI Master/Slave Mode Select 0 = Slave mode (default). 1 = Master mode. CPOL, CPHA SPI Clock Polarity and Clock Phase. See SPI Data Rate and Clock Formats. SSOE Slave Select Output Enable The slave select output feature allows the SS* pin to act as an input or output when in master mode. The SSOE, MODFEN in SPICR2 and MSTR bits determine the operation as shown in Table 14-4 . See SPI Mode Faults. Table 14-4 SS* Input/Output Selection MODFEN SSOE Master Mode (MSTR=1) Slave Mode (MSTR=0) 0 0 1 1 0 1 0 1 SS* not used by SPI SS* not used by SPI SS* input with MODF feature SS* is slave select output SS* input SS* input SS* input SS* input LSBFE SPI Least Significant Bit First 0 = Data are transferred most significant bit first (default). 1 = Date are transferred least significant bit first.Chapter 14 – M68HCS12 Serial I/O 14-19 SPICR2 – Base + $00D9 – SPI Control Register 2 Bit 7 6 5 4 3 2 1 0 Read: 0 0 0 0 Write: MODFEN BIDIROE SPISWAI SPC0 Reset: 0 0 0 0 0 0 0 0 = reserved, unimplemented or cannot be written to. Read: Anytime. Write: Anytime. MODFEN Mode Fault Enable 0 = SS* port pin is not used by the SPI (default). 1 = SS* port pin is used with the mode fault feature. See Table 14-4 and SPI Mode Faults. BIDIROE Output Enable in Bidirectional Mode 0 = Output buffer is disabled (default). 1 = Output buffer is enabled. See SPI Master and Slave Mode. SPISWAI SPI Stop in Wait Mode 0 = SPI clock