Processor: Datapath and ControlIntroduction• Clock cycle time and number of cpi are determined by processor implementation• Datapath and control• Effect of different implementation choices on clock rate and cpi• Implementation overview– Two identical first step for every instruction1. Send pc to memory and fetch the instruction from that location2. Read one or two registers, selected by fields of instruction opcode (one register for lw, two for mostof the other instructions)– Perform the actions to accomplish the instruction∗ Actions are largely the same, independent of exact opcode∗ Holds for each instruction class: memory reference, arithmetic-logic, and branch– All instruction classes use alu after reading registers∗ Memory reference instructions use alu for address calculations∗ Arithmetic-logic instructions use alu for operation execution∗ Branch instructions use alu for comparison– Post-alu execution of instructions∗ Memory-reference instruction needs to access memory for load or store∗ Arithmetic-logic instruction must write data to a register∗ Branch instruction needs to change the pc for next instruction address based on comparison– Figure 5.1∗ High level view of a mips implementation• Logic convention and clocking– Designer may need to change the mapping between a logically true or false signal and the high or lowvoltage level– In some parts of a design, a signal that is logically asserted may be electrically low while in other parts,an electrically high signal is assertedasserted indicates a signal that is logically highassert indicates a signal that should be driven logically high– Functional unit in mips implementation has two different logic elements1. Combinational elements∗ Elements that operate on data values∗ Output depends only on the current inputs∗ No internal storage∗ Exemplified by circuitry to perform arithmetic operations2. State elements∗ Elements that contain state, or internal storage∗ Characterize the state of the machine∗ If machine loses power but these elements can be restored, we can restart the machine from thestate at which the power was lost∗ Instructions and data memories, as well as registersProcessor: Datapath and Control 2∗ At least two inputs and one output∗ Inputs are data value to be written into the element and the clock to determine when the datavalue is written∗ Output is the value that was written during an earlier clock cycle∗ One of the logically simplest state elements is a D-type flip flop that has exactly two inputs andone output∗ Other state elements used in mips implementation are memories and registers– Logic components containing state are called sequential because their output depends on both internalstate and inputs• Clocking methodology– Defines when signals can be read or written– Concurrency issue; read at the same time as write– Edge-triggered clocking methodology∗ Any values are to be updated only on a clock edge∗ State elements update their stored value on the clock edge∗ Figure 5.2∗ Any collection of combinational logic must have its inputs coming from a set of state elements andits outputs written into a set of state elements∗ Inputs are values written in a previous clock cycle∗ Outputs are values to be used in a following clock cycle∗ Length of the clock cycle is the time taken by the system to go from one element to the other∗ If a state element is not updated on every edge, an explicit write control signal is required· State element is updated only when the write control signal is asserted and a clock edge occurs– Figure 5.3∗ Read, operate, and write can be achieved in the same clock cycle∗ No feedback within a single clock cycle– All state and logic elements have 32-bit wide inputs and outputs∗ Buses are signals wider than 1 bit∗ Several buses can be combined to make a wider bus• mips subset implementation– Simple implementation using a single clock cycle for every instruction– Not practical∗ Does not allow different instruction classes to take different number of clock cycles that may be shorterBuilding a datapath• Major components required to execute each class of mips instruction– State element memory unit∗ Holds and supplies instructions given an address– State element pc∗ Holds the address of next instruction to be executed– Combinational logic adder∗ Makes pc point to the next instruction’s addressProcessor: Datapath and Control 3∗ Built from the alu– Figure 5.4• Instruction execution– Fetch the instruction from memory– Increment pc by 4– Figure 5.5• R-format instructions– Includes arithmetic-logic instructions, such as add, sub, slt, and, and or– Read two registers, perform an operation, and write result to a third register– Registers are stored in a structure called register file∗ Register file has two read ports and one write port∗ For each data word to be read from [written to] register file, we need· Register number to be read from [written to]· Output from [Input to] the register file to carry the value being read [written]∗ Writes are asserted by a write control signal, for a write to occur at a clock edge∗ Figure 5.6∗ Four inputs – three to identify registers, one for data· Inputs to identify registers are 5-bit wide· Data input is 32-bits∗ Two 32-bit outputs for data– alu is controlled by a 3-bit signal∗ 1-bit bnegate and 2-bit operation∗ Figure 4.19∗ Signals are given byalu control lines Function0 00 and0 01 or0 10 add1 10 sub1 11 slt∗ Two 32-bit inputs and 1 32-bit output– Datapath for R-type instructions∗ Figure 5.7– lw and sw instructions∗ General format: lw $t1, offset ( $t2 )∗ Compute the memory address by adding the base register ($t2) to the 16-bit signed offset field∗ For sw, value to be stored must be read from register file ($t1)∗ For lw, value read from memory must be stored to register file in t1∗ Need the register file and alu∗ Also need a unit to sign extend 16-bit offset to 32-bit signed value, and a data memory unit (Figure5.8)∗ Data memory· Must be written on sw· Must have both read and write control signalProcessor: Datapath and Control 4· Must have an address input· Must have a data input∗ Figure 5.9– beq instruction∗ beq $t1, $t2, offset∗ Three operands: two registers to compare for equality and a 16-bit offset to compute branch addressrelative to current