An Effective Hybrid Transactional Memory Systemwith Strong Isolation GuaranteesChi Cao Minh, Martin Trautmann, JaeWoong Chung,Austen McDonald, Nathan Bronson, Jared Casper,Christos Kozyrakis, Kunle OlukotunComputer Systems LaboratoryStanford Universityhttp://tcc.stanford.edu{caominh, mat42, jwchung, austenmc, nbronson, jaredc, kozyraki, kunle}@stanford.eduABSTRACTWe propose signature-accelerated transactional memory (SigTM),a hybrid TM system that reduces the overhead of software trans-actions. SigTM uses hardware signatures to track the read-set andwrite-set for pending transactions and perform conflict detectionbetween concurrent threads. All other transactional functionality,including data versioning, is implemented in software. Unlike pre-viously proposed hybrid TM systems, SigTM requires no modifi-cations to the hardware caches, which reduces hardware cost andsimplifies support for nested transactions and multithreaded pro-cessor cores. SigTM is also the first hybrid TM system to providestrong isolation guarantees between transactional blocks and non-transactional accesses without additional read and write barriers innon-transactional code.Using a set of parallel programs that make frequent use of coarse-grain transactions, we show that SigTM accelerates software trans-actions by 30% to 280%. For certain workloads, SigTM can matchthe performance of a full-featured hardware TM system, while forworkloads with large read-sets it can be up to two times slower.Overall, we show that SigTM combines the performance character-istics and strong isolation guarantees of hardware TM implementa-tions with the low cost and flexibility of software TM systems.Categories and Subject Descriptors: C.1.2 [Processor Architec-tures]: Multiple Data Stream Architectures – MIMD processors;D.1.3 [Programming Techniques]: Concurrent Programming – par-allel programmingGeneral Terms: Performance, Design, LanguagesKeywords: Transactional Memory, Strong Isolation, Multi-coreArchitectures, Parallel Programming1. INTRODUCTIONTransactional Memory (TM) [16, 1] is emerging as a promis-ing technology to address the difficulty of parallel programmingPermission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on the first page. To copy otherwise, torepublish, to post on servers or to redistribute to lists, requires prior specificpermission and/or a fee.ISCA’07, June 9–13, 2007, San Diego, California, USA.Copyright 2007 ACM 978-1-59593-706-3/07/0006 ...$5.00.for multi-core chips. With TM, programmers simply declare thatcode blocks operating on shared data should execute as atomic andisolated transactions with respect to all other code. Concurrencycontrol as multiple transactions execute in parallel is the responsi-bility of the system.Transactional memory can be implemented in hardware (HTM)or software (STM). HTM systems use hardware caches to track thedata read or written by each transaction and leverage the cachecoherence protocol to detect conflicts between concurrent transac-tions [13, 20]. The advantage of hardware support is low over-head. Transactional bookkeeping takes place transparently as theprocessor executes load and store instructions. The disadvantageof HTM is complexity and cost, as the caches and the coherenceprotocol must be redesigned. It is also difficult to justify new hard-ware features without significant experience with a large body oftransactional software. STM systems implement all bookkeepingin software using instrumentation code (read and write barriers)and software data structures [14, 22, 11, 15]. STM frameworks runon existing hardware and can be flexibly modified to introduce newfeatures, provide language support, or adapt to specific applicationcharacteristics. The disadvantage of the software-only approachis the runtime overhead due to transactional bookkeeping. Eventhough the instrumentation code can be optimized by compilers [2,15], STM can still slow down each thread by 40% or more.Apart from the cost/performance tradeoff, there are important se-mantic differences between HTM and STM. HTM systems supportstrong isolation, which implies that transactional blocks are iso-lated from non-transactional accesses [18]. There is also a consis-tent ordering between committed transactions and non-transactionalaccesses. In contrast, high-performance STM systems do not sup-port strong isolation because it requires read and write barriers innon-transactional code and leads to additional runtime overhead.As as result, STM systems may produce incorrect or unpredictableresults even for simple parallel programs that would work correctlywith lock-based synchronization [18, 12, 24].This paper introduces signature-accelerated TM (SigTM), a hy-brid transactional memory implementation that reduces the over-head of software transactions and guarantees strong isolation be-tween transactional and non-transactional code. SigTM uses hard-ware signatures to conservatively represent the transaction read-setand write-set. Conflict detection and strong isolation are supportedby looking up coherence requests in the hardware signatures [5].All other functionality, including transactional versioning, commit,and rollback, is implemented in software. Unlike previously pro-posed hybrid schemes [17, 10, 23], SigTM requires no modifica-tions to hardware caches, which reduces SigTM’s hardware cost,simplifies crucial features (support for OS events, nested trans-actions, and multithreading), and eliminates negative interferencewith other cache operations (prefetching and speculative accesses).Moreover, SigTM is a stand-alone hybrid TM that does not requiretwo operation modes or two code paths. SigTM is also the first hy-brid TM system to implement strong isolation without additionalbarriers in non-transactional code.The specific contributions of this work are:• We describe the hardware and software components of SigTM,a hybrid transactional memory system that uses hardwaresignatures for read-set and write-set tracking. SigTM im-proves the performance of software transactions while pro-viding strong isolation guarantees.• We compare SigTM to STM and HTM systems using a set ofparallel applications that make frequent use of coarse-graintransactions. We show that SigTM outperforms software-only TM by 30% to 280%.