Mesochronous clocking and communication in on-chip networksDaniel WiklundDept. of Electrical EngineeringLinköping UniversityS-581 83 Linköping, [email protected] networks are becoming a popular researchtopic, both in industry and universities. Many re-searchers assume a fully synchronous or globallyasynchronous, locally synchronous model of opera-tion for the network. We have previously proposedthe use of mesochronous communication within thenetwork as a simple and robust way to get around theproblems of fully synchronous operation.The mesochronous communication technique issimple both in understanding and implementationand allows for significant freedom in design, place-ment, and inter-subsystem delays.This paper presents the concept of mesochronouscommunication and clocking. It further introduces apossible implementation for the network componentinterconnections using mesochronous communicationwith an integrated clock distribution mechanism. Thisimplementation is then analyzed from a functionalperspective.1. INTRODUCTIONDuring the last few years there has been a signifi-cant increase in popularity of research on on-chip net-works. With many architectural proposals there arealso the need to understand the method of commu-nication within the network on lower levels. A com-mon assumption is that the network is run either glob-ally synchronously over the chip or that it is run com-pletely asynchronously [1, 2].In principle there are three methods to use for syn-chronization of a system. The most commonly usedtoday is the synchronous system where a global clockis distributed over the system with low skew. ThisDaniel Wiklund is a Ph.D. student at the division of ComputerEngineering, Dept of Electrical Engineering, Linköping University.This work is funded by the STRINGENT electronics center. Thiswork is based on an idea by Prof. Christer Svensson, Electronic De-vices, Dept of Electrical Engineering, Linköping University.clock is then used to time all the events and transac-tions in the system.Another method that is popular in research and ex-treme low power products is to run the system com-pletely asynchronous. Completely asynchronous sys-tems need to use handshaking or special timing cir-cuitry for both computations and communications inorder to keep synchronization within the system.The third method is to use blocks that are syn-chronous but communicate asynchronously, betterknown as the globally asynchronous, locally syn-chronous (GALS) methodology. With the current in-crease in the number of different clock domains usedon a single chip this is a very promising overall tech-nique to use for IP block integration.If a subsystem is distributed over a large area withina chip there is also the possibility to use a methodthat is somewhat in between the previously men-tioned methods. Here there is a common clock thatis distributed to the system without concern aboutthe phase difference in different parts of the system.Parts of the system may run as synchronous subsys-tems and can be designed using the accepted standardmethods of today.The communication between the subsystems is thendone in much the same way as for a fully synchronoussystem. The primary difference is that the incomingdata to a subsystem has to be aligned to the local clockphase. Since the clock rate is the same for the entiresystem this can be performed with a simple retimingcircuitry.We have previously proposed an on-chip network[3] and suggested it should use a mesochronous com-munication and clocking scheme for internal commu-nication [4]. This paper presents a possible solutionfor the mesochronous communication and clock dis-tribution between the network components.NI NININIRouterRouter RouterRouterIP blockIP block IP blockIP blockLinkLinkFig. 1. Section of a mesh style on-chip network.2. CLOCK DISTRIBUTION IN ON-CHIPNETWORKSAssuming that the components of the on-chip net-work is implemented using a method that is not fullyasynchronous, a clock is needed in each router andnetwork interface. If the system is to use a glob-ally synchronous model the distributed clock has tohave low skew between the connected neighbors inthe network but it is possible to allow significantlymore clock skew across longer distances in the net-work. Since there are only fairly local links in the net-work, see figure 1, this is a feasible solution for net-works with low clock rate (up to a few hundred MHz).A fully asynchronous solution of course do not needa clock distribution at all. There is also the pos-sibility to use a mixed system based on the glob-ally asynchronous and locally synchronous (GALS)scheme, i.e. the routers and network interfaces arerun synchronous internally and asynchronous exter-nally. This method requires the distribution of a clockto every network component but there is no specificdemands on clock skew or even difference in clock fre-quency between the components.3. MESOCHRONOUS CLOCKINGOur proposed solution is to use mesochronous clock-ing, i.e. using the same frequency but with unknownphase. There are two basic methods for communica-tion between subsystems when using mesochronousclocking. The first is to recognize and handle the situ-ation when metastable conditions may occur [5]. Thedetection of this kind of possibly metastable condi-216 DataFrameReverse ctrlReverse ctrlFrameData162Two linksNetwork componentNetwork componentFig. 2. Basic signals for one undirectional internal net-work link.tion gives rise to a 180 degree shift in the local clockphase used for synchronizing the incoming data. Thismethod has the advantage of not needing any extrawiring for the synchronization but is bad since theclock phase difference may be very close to where themetastable conditions will occur.The second approach is to keep as far away from themetastable case by analyzing the incoming data phaseor by providing a timing signal along with the datasignals that can be used to estimate the phase differ-ence.One of the most basic requirements for uncon-strained mesochronous clocking and communicationis that there must be no special timing requirementson the communication. This means that things likelow level flow control for the communication may beimpossible to implement. The subsystems then haveto be designed in such a way that this low level flowcontrol is not necessary.We propose to use the second approach where ev-ery network component is built using the well-knownmethodology for fully synchronous systems