Sequential LogicOutput based on input values and their sequencing, i.e., their history (timing is important!)Will often use trigger signals, called ‘clock’ (Clk) signals to trigger eventsFlip-Flops (also known as bi-stables or latches)Devices that can store and switch between binary states, 0 and 1Fundamental building block of all semiconductor memory and processing in digital computersMade up of logic gates with feedback (some outputs are fed back to inputs of other gates)RS Flip-FlopS stand for ‘set’R stands for ‘reset’Q and are complementary outputsTruth tableInputsOutputsSRQ00Q0100111NANA means ‘not allowed’Triggering Flip-FlopsOften important to synchronize changes in state of multiple flip-flops on clock signalPositive edge-triggered means that device responds to O-1 transition of clock pulseNegative edge-triggered means that device responds to 1-0 transition of clock pulsePositive edge-triggered RS flip-flop (wedge shape at clock input means ‘edge-triggered’)InputsClkOutputsSRQ00Q01010010111NANA means ‘not allowed’Level-triggered devices (no wedge shape at clock input) respond to input when clock signal is high (or low if Clk input is inverted). When clock signal goes low, output is held.D Flip-Flop (ex. 7474)Single input is stored and presented to Q on edge of clock pulseEx. Positive edge-triggered D flip-flopPresetClearDClkQ110011111011x0Q011x1Q001xx1010xx0100xxNAPreset pulled low (“active low”) will set Q to 1Clear pulled low (“active low”) will clear or reset Q to 0Ex. 7475 ‘latch’ (quad D flip-flops grouped in pairs with separate enable signals 2, two-bit data storage)JK Flip-Flop (ex. 7476)Like RS flip-flop, where J is like S and K is like R, but can have both J and K high. This will cause output to toggle (change state)Ex. Positive edge-triggered JK flip-flopPresetClearJKClkQ1100Q01101011110101111Toggle11xx0, 1Q001xxx1010xxx0100xxxNA1Sequential LogicOutput based on input values and their sequencing, i.e., their history (timing is important!)Will often use trigger signals, called ‘clock’ (Clk) signals to trigger eventsFlip-Flops (also known as bi-stables or latches)Devices that can store and switch between binary states, 0 and 1Fundamental building block of all semiconductor memory and processing in digital computersMade up of logic gates with feedback (some outputs are fed back to inputs of other gates)RS Flip-FlopS stand for ‘set’R stands for ‘reset’Q and Q are complementary outputsTruth tableInputs OutputsS R QQ0 0 Q00Q1 00 11 1 NANA means ‘not allowed’Triggering Flip-FlopsOften important to synchronize changes in state of multiple flip-flops on clock signalPositive edge-triggered means that device responds to O-1 transition of clock pulseNegative edge-triggered means that device responds to 1-0 transition of clock pulsePositive edge-triggered RS flip-flop (wedge shape at clock input means ‘edge-triggered’)Inputs Clk OutputsS RQQ0 0Q00Q1 01 00 10 11 1 NANA means ‘not allowed’ means activated on rising edge of clock signal (positive edge)Level-triggered devices (no wedge shape at clock input) respond to input when clock signal is high (or lowif Clk input is inverted). When clock signal goes low, output is held.A ‘bubble’ means active low (for level triggered) or negative edge (for edge triggered).BJ Furman Sequential Logic handout.doc 28APR2011RSQRQRSQRQRSRQClkTimingRSQQ10101010Time2D Flip-Flop (ex. 7474)Single input is stored and presented to Q on edge of clock pulseEx. Positive edge-triggered D flip-flopPreset Clear D Clk QQ1 1 00 11 1 11 01 1 x 0 Q00Q1 1 x 1 Q00Q0 1 x x 1 01 0 x x 0 10 0 x x NAPreset pulled low (“active low”) will set Q to 1Clear pulled low (“active low”) will clear or reset Q to 0D flip flops are used for data registers (like DDRx in ATmega microcontrollers). Sometimes theyare called “data latches”Ex. 7475 ‘latch’ (quad D flip-flops grouped in pairs with separate enable signals 2, two-bit data storage)JK Flip-Flop (ex. 7476)Like RS flip-flop, where J is like S and K is like R, but can have both J and K high. This will cause output to toggle (change state)Ex. Positive edge-triggered JK flip-flopPreset Clear J K Clk QQ1 1 0 0Q00Q1 1 0 10 11 1 1 01 01 1 1 1Toggle1 1 x x 0, 1 Q00Q0 1 x x x 1 01 0 x x x 0 10 0 x x x NABJ Furman Sequential Logic handout.doc 28APR2011ClkDRQPresetClearClkJRQPresetClearK3Figures from Alciatore and Histand, Introduction to Mechatronics and Measurement Systems, 3rded., McGraw-Hill, NY, 2007.BJ Furman Sequential Logic handout.doc 28APR20114BJ Furman Sequential Logic handout.doc 28APR20115BJ Furman Sequential Logic handout.doc
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