Sigma-Delta Fractional-N Frequency SynthesisNote: Much of this material is taken from MITOpenCourseWarehttp://ocw.mit.eduCourse: 6.976OutlineBandwidth Constraints for Integer-N SynthesizersBandwidth Versus Frequency ResolutionIncreasing Resolution in Integer-N SynthesizersThe Issue of NoiseBackground: Classical Linearized PLL ModelBackground: Classical Linearized PLL ModelParameterized Version of Classical ModelModeling PFD Noise MultiplicationFractional-N Frequency SynthesizersClassical Fractional-N Synthesizer ArchitectureAccumulator OperationFractional-N Synthesizer Signals with N = 4.25The Issue of Spurious TonesThe Phase Interpolation TechniqueThe Problem With Phase InterpolationIs There a Better Way?A Better Dithering Method: Sigma-Delta ModulationLinearized Model of Sigma-Delta ModulatorExample: Cutler Sigma-Delta TopologyLinearized Model of Cutler TopologyCalculation of Signal and Noise Transfer FunctionsChoice of H(z)Example: First Order Sigma-Delta ModulatorExample: Second Order Sigma-Delta ModulatorExample: Third Order Sigma-Delta ModulatorObservationsWarning: Higher Order Modulators May Still Have TonesDitherCascaded Sigma-Delta Modulator TopologiesMASH topologyCalculation of STF and NTF for MASH topologyCalculation of STF and NTF for MASH topologySigma-Delta Frequency SynthesizersBackground: The Need for A Better PLL ModelA PLL Model Accommodating Divide Value VariationsParameterized Version of New ModelDivider Impact For Classical Vs Fractional-N ApproachesFocus on Sigma-Delta Frequency SynthesizerQuantifying the Quantization Noise ImpactSummary: Sources of Phase Noise in ?? SynthesisA quick note on the linearized modelA Well Designed Sigma-Delta SynthesizerImpact of Increased Sigma-Delta OrderImpact of Increased PLL BandwidthCan the Quantization Noise Impact be reduced?Impact of Increasing the PLL BandwidthMethod 1 of Reducing Quantization NoiseMethod 2 of Reducing Quantization NoiseComparison of ApproachesComparison of ApproachesTwo Recent Phase Interpolation MethodsKey Element: A PFD/DAC StructureApply Phase Shift to Two out of the Four PFD’sApply Phase Shift to Three out of the Four PFD’sActual PFD/DAC ImplementationA quick note on simulationPLL Design AssistantCppSim – A Fast Behavioral SimulatorGoal: Wide bandwidth, low noise synthesizer!Goal: Wide bandwidth, low noise synthesizer!Other Issues to ConsiderConclusionsAppendixSigma-Delta Fractional-N Frequency SynthesisScott MeningerMichael PerrottMassachusetts Institute of TechnologyJune 7, 2004Copyright © 2004 by Michael H. PerrottAll rights reserved.Note: Much of this material is taken from MITOpenCourseWarehttp://ocw.mit.eduCourse: 6.976Outline Integer-N synthesis- Bandwidth constraints Fractional-N synthesis- Issue of fractional spurs Σ∆ Fractional-N Synthesis- Quantization noise impact on the PLL Recent developments for lowering the impact of quantization noise Conclusions Q&ABandwidth Constraints for Integer-N SynthesizersPFDLoopFilter(1/T = 20 MHz)ref(t) out(t)N[k]Divider1/TLoop FilterBandwidth << 1/T PFD output has a periodicity of 1/T- 1/T = reference frequency Loop filter must have a bandwidth << 1/T- PFD output pulses must be filtered out and average value extractedClosed loop PLL bandwidth often chosen to be afactor of ten lower than 1/TBandwidth Versus Frequency ResolutionPFDLoopFilter1.80 1.82GHz(1/T = 20 MHz)ref(t) out(t)out(t)Sout(f)N[k]N[k]9091Dividerfrequency resolution = 1/T1/T1/TLoop FilterBandwidth << 1/T Frequency resolution set by reference frequency (1/T)- Higher resolution achieved by lowering 1/TIncreasing Resolution in Integer-N SynthesizersPFDLoopFilter1.80 1.8002GHz(1/T = 200 kHz)ref(t)out(t)out(t)Sout(f)N[k]N[k]90009001Dividerfrequency resolution = 1/T1/T1/TLoop FilterBandwidth << 1/T10020 MHz Use a reference divider to achieve lower 1/T- Leads to a low PLL bandwidth ( < 20 kHz here )The Issue of NoisePFDLoopFilter1.80 1.8002GHz(1/T = 200 kHz)ref(t)out(t)out(t)Sout(f)N[k]N[k]90009001Dividerfrequency resolution = 1/T1/T1/TLoop FilterBandwidth << 1/T10020 MHz Lower 1/T leads to higher divide value- Increases PFD noise at synthesizer outputBackground: Classical Linearized PLL ModelΦdiv[k]Φref[k]KVjfv(t)Φout(t)H(f)1N παe(t)Φvn(t)en(t)IcpVCO-referredNoisef0SEn(f)PFD-referredNoise1/Tf0SΦvn(f)-20 dB/decPFDChargePumpLoopFilterDividerVCON[k] Classical PLL model- Predicts impact of PFD and VCO referred noise sources- Does not allow straightforward modeling of impact due to dynamic divide value variations More on this shortly …Background: Classical Linearized PLL ModelΦdiv[k]Φref[k]KVjfv(t)Φout(t)H(f)1N παe(t)Φvn(t)en(t)IcpVCO-referredNoisef0SEn(f)PFD-referredNoise1/Tf0SΦvn(f)-20 dB/decPFDChargePumpLoopFilterDividerVCON[k] Parameterizing in terms of G(f) helps visualize the nature (high-pass or low-pass) and gain of the noise transfer functionsParameterized Version of Classical ModelΦvn(t)en(t)Φout(t)Φc(t)Φn(t)Φnvco(t)Φnpfd(t)fo1-G(f)foG(f)2πNαVCO-referredNoisef0SEn(f)PFD-referredNoise1/Tf0SΦvn(f)-20 dB/decDivider Controlof Frequency Setting(assume noiseless for now) G(f) represents the PLL closed loop dynamics G(f) is low-pass Nature of noise transfer very easily seen from the parameterized modelModeling PFD Noise Multiplication PFD spectral density multiplied by N2before influencing PLL output phase noiseΦvn(t)en(t)Φout(t)Φc(t)Φn(t)Φnvco(t)Φnpfd(t)fo1-G(f)foG(f) πNαVCO-referredNoisef0SEn(f)PFD-referredNoise1/Tf0SΦvn(f)-20 dB/decDivider Controlof Frequency Setting(assume noiseless for now)Sen(f) πNα2Radians2/HzSΦvn(f)f(fo)opt0Radians2/HzSΦnpfd(f)SΦnvco(f)f(fo)opt0High divide values high phase noise at low frequenciesFractional-N Frequency Synthesizers Break constraint that divide value be integer- Dither divide value dynamically to achieve fractional values- Frequency resolution is now arbitrary regardless of 1/T Want high 1/T to allow a high PLL bandwidthDitheringModulatorPFDLoopFilter1.80 1.82GHz(1/T = 20 MHz)ref(t)out(t)out(t)Sout(f)N[k]Nsd[k]Nsd[k]90909191Dividerfrequency resolution << 1/T1/TClassical Fractional-N Synthesizer Architecture1-bitPFDLoopFilterref(t)div(t)out(t)frac[k]AccumulatorN/N+1carry_out[k]e(t)Nsd[k] = N + frac[k] Use an accumulator to perform dithering operation- Fractional input value fed into accumulator- Carry out bit of accumulator fed into dividerAccumulator Operationresidue[k]carry_out[k]frac[k]