ME 141B: The MEMS Class Introduction to MEMS and MEMS Design Sumita Pennathur UCSBMicrofabrication Outline • Substrates – Si, SOI, Fused quartz, etc.. • Lithography and patterning • Doping • Thin Films • Etching • Wafer Bonding • Surface Micromachining • Process Integration 10/5/10 2/45Creating thin (and thick) films • Many techniques to choose from • Differences:  Front or back end processes  Quality of resulting films (electrical properties, etch selectivity, defects, residual stress)  Conformality  Deposition rate, cost • Physical techniques  Material is removed from a source, carried to the substrate, and dropped there • Chemical Techniques  Reactants are transported to the substrate, a chemical reaction occurs, and the product deposit on the substrate to form the desired film 10/5/10 3/45Taxonomy of deposition techniques • Chemical  Thermal Oxidation  Chemical Vapor Deposition (CVD) • Low Pressure (LPCVD), Atomspheric pressure (APCVD), Plasma Enhanced (PECVD)  Epitaxy  Electrodeposition (Electroplating) • Physical  Physical Vapor Deposition (PVD) • Evaporation • Sputtering  Spin-casting 10/5/10 4/45Oxidation I • Silicon forms a high quality, stable oxide  How it works: • Oxygen diffuses through oxide to SI/oxide interface • SI + O2 + high temperature (~1100) furnace  SiO2 • Some Si is consumed  Rate determined by diffusion of oxygen through oxide  Diffusion limits practical oxide thickness to < 2 um  A key front end process 10/5/10 5/45Oxidation II • Dry Oxidation (O2)  High quality, slow oxidation rate, smaller maximum thickness (i.e. gate oxide) • Wet Oxidation (steam)  H2 to speed the diffusion  Lower quality, faster oxidation rate • The Deal-Grove model describe the kinetics of oxidation quite well for oxides greater in thickness that about 30nm 10/5/10 6/45The Deal-Grove Model 10/5/10 7/45Local Oxidation • Oxidation can be masked locally by an oxidation barrier, such as silicon nitride • Oxide undercuts edge of mask layer to form a “bird’s beak” • Oxidation followed by an oxide etch can also be used to sharpen silicon features 10/5/10 8/45Chemical Vapor Deposition (CVD)• How CVD works:  Gaseous reactants, often at low pressure  Long mean free path; reactants reach substrate  Reactants react and deposit products on the substrate  Unlike Oxidation, does not consume substrate material • Energy sources facilitate CVD reactions:  High temperature, plasma, laser • Processing temperatures vary widely • Commonly deposited films: Oxide, silicon nitride, polysilicon • CVD results depend on pressures, gas flows, temperature  Film composition, uniformity, deposition rate, and electrical and mechanical characteristics can vary 10/5/10 9/45Some reasons to use CVD • Oxide formation:  To get a thicker layer than thermal oxidation can provide  To create oxide on a wafer that can’t withstand high temperatures (for example because of metal features)  To create oxide on top of a material that is not silicon • For film formation in general  To tailor the film properties (like form stress) by adjusting pressures, flow rates, external energy supply, ratios of different precursor gases (to adjust proportions of different materials in the final product)  Conformailty : (more of less) even coating on all surfaces • Drawbacks:  Films deposited at low temperature are often lower quality than high temp versions, and have less predictable properties  Flammable, toxic or corrosive source gases 10/5/10 10/45Thick Film Formation • CVD is a common MEMS tool for creating thick films on the wafer surface  In practice, film stress limits thickness (film delamination or cracking, or curvature of underlying structures)  Can deposit thick oxides; nitrides are still typically submicron  Must anneal deposited oxides for some applications – lose low stress property on anneal 10/5/10 11/45CVD enables conformal coating10/5/10 12/45LPCVD Polysilicon • Amorphous at lower deposition temperatures and high deposition rates  Typical temperature: ~590 C • Polycrystalline at higher deposition temperatures and lower deposition rates  Typical temperature: ~625 C • Grain size and structure depend on detailed deposition conditions  E.g. thicker films  larger grains • Structure, electrical properties, and mechanical properties also vary with post-deposition thermal processing  Grain growth  Dpoant activation or diffusion 10/5/10 13/45Polysilicon stress depends on deposition rates 10/5/10 14/45Epitaxy • CVD deposition process in which atoms move to lattice sites, continuing the substrate’s crystal structure  Homoepitaxy: same material, i.e. Si on Si  Heteroepitaxy: different materials, i.e. AlGaAs, on GaAs • How it happens  Slow deposition rate (enough time to find a lattice site)  High Temperature (enough energy to move a lattice site) • Selective epitaxy is possible through masking • Can grow a doped Si layer of known thickness 10/5/10 15/45Electroplating: basics • Pass a current through an aqueous metal solution  Anode is made of the meta that you want to deposit  Cathode is the conductive seed material on your wafer  Positive metal ions travel to the negatively charged cathode on your wafer and deposit there • Preparing your wafer  If you want to plate metal in some places and not in others, you will need a patterned metal seed layer (and typically a “sticky” metal adhesion layer under that)  For very short features, just plate onto the seed layer  For taller features, need to plate into a mold  Molds can be photoresist, silicon, SU-8, et.. Depending on the needs of your device 10/5/10 16/45Electroplating 10/5/10 17/45Electroplating realities 10/5/10 18/45Conformality and keyholes • To lowest order, conformal films coat sidewalls and horizontal surfaces at the same rate • But high aspect ratio trenches are prone to keyholes (CVD, electroplating, etc..) 10/5/10 19/45Physical Vapor Deposition • Remove materials from a solid