On-chip networks for System-on-chipsSoC Communication Architectures: BackgroundCurrently used communication architectures on SoCStatic Priority Based Shared BusTDMA Based Shared BusSlide 6Problems with Other ArchitecturesExamples of High-Performance Communication Architecture for SoC DesignsLotteryBusSlide 10How it worksLottery manager for static LOTTERYBUS architectureLottery manager for dynamic LOTTERYBUS architectureAdvantages of LotteryBusSonics µNetworkSonics DesignOverview of µNetworkSystem Based on Sonics µNetworkSonics µNetwork ComponentsSiliconBackplane µNetwork (On-Chip Interconnect)Open Core ProtocolMultiChip µNetwork (Off-Chip Interconnect)Other Examples of Communication Architecture for SOC DesignsReferences1On-chip networks for System-on-chipsEmbedded System DesignYuping DongShiva Navab2SoC Communication Architectures: BackgroundkeywordsMastersSlavesChannelBridgesBus arbiters3Currently used communication architectures on SoCStatic Priority Based Shared Bus Time Division Multiplexing Access (TDMA) Shared BusRef: Lottery Bus Paper 4Static Priority Based Shared BusRef: Lottery Bus Paper 5TDMA Based Shared BusRef: Lottery Bus Paper 6TDMA Based Shared Bus7Problems with Other ArchitecturesStatic Priority Based Shared Buslack of control over the allocation of communication bandwidth to different system components or data flows TDMA Based Shared Bussignificant latencies resulting from variations in the time-profile of the communication requests8Examples of High-Performance Communication Architecture for SoC DesignsLotteryBusSonics µNetwork9LotteryBusA New High-Performance Communication Architecture for complex System-on-Chip Designscontrol over the fraction of communication bandwidthfast execution (low latencies)Ref: Lottery Bus Paper 10LotteryBusRef: Lottery Bus Paper 11How it worksThe probability that bus is granted to Ci :The probability that a task with t tickets can access the bus after n lottery drawings:Ref: Lottery Bus Paper 12Lottery manager for static LOTTERYBUS architectureRef: Lottery Bus Paper 13Lottery manager for dynamic LOTTERYBUS architectureRef: Lottery Bus Paper 14Advantages of LotteryBus15Sonics µNetworkSonics INC 16Sonics DesignCore DecouplingUnique arbitration mechanismSonics INC 17Overview of µNetworkSonics INC 18System Based on Sonics µNetworkSonics INC 19Sonics µNetwork ComponentsSonics INC 20SiliconBackplane µNetwork(On-Chip Interconnect)Sonics INC 21Open Core Protocol22MultiChip µNetwork (Off-Chip Interconnect)Bandwidth AllocationConnectsIntegrated Signaling Mechanism23Other Examples of Communication Architecture for SOC DesignsAMBA BusARM-based microprocessorsVSIA BusVirtual Socket Interface Alliance24ReferencesLOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip DesignsyKanishka Lahiri zAnand Raghunathan zGanesh Lakshminarayanay http://citeseer.nj.nec.com/447789.html Sonics' SiliconBackplane µNetwork & Open Core Protocolhttp://www.sonicsinc.comhttp://www.sonicsinc.com/Pages/Networks.htmlhttp://www.sonicsinc.com/Documents/AMBAFlynn, D. AMBA: enabling reusable on-chip designs. IEEE Micro, vol.17, (no.4), IEEE, July-Aug. 1997. p.20-7. http://ielimg.ihs.com/iel4/40/13385/00612211.pdf VSIA's On-chip