IP Based DesignIntroductionCore TypesDesign IssuesIP Specification – JAVACAD DOMIPCHINOOK - Modal ProcessesControl Composition - Wrist WatchMode Manager SynthesisCore ImplementationModelsCommunication SynthesisSlide 12Interface SynthesisProtocol specificationProtocol specification exampleSynthesis AlgorithmSimulations and VerificationsConclusionReferences01/13/19 1IP Based DesignJin-seong Jeong and Ram KumarEE202A Fall 2001Student Presentation01/13/19 2IntroductionIP – Intellectual PropertyPre-designedPre-verifiedRe-usableH/W S/W Functional BlocksExamplesProcessor – Leon Sparc, IBM PPCMultimedia – MPEG Decoder, JPEG CompressionControllers – USB, PCINetworking - Ethernet01/13/19 3Core TypesSoft CoresHDL DescriptionFlexible – Can be changed to suit an applicationTechnology Independent – Can be re-synthesized across processesFirm CoresGate-level netlists to be placed and routedHard CoresReady to useInclude layout and timing (Tech. Dependant)Mostly processors and memory01/13/19 4Design IssuesIP SpecificationIP ImplementationReusabilityCustomizable/PortableValidationCommunication/Interface SynthesisSocketing StandardsCommunication between software modulesSimulation and VerificationIP Protection01/13/19 5IP Specification – JAVACAD DOMIP ComponentIP ComponentIP RepositoryIP ImplementationIP SpecificationIP ComponentBehavior CodeIP ImplementationRTL CodeIP SpecificationAreaClockPowerThroughputTiming ConstraintsPort MapPORT MAPClockInput PortOutput PortInOut PortPORT LISTPort APort BTIMINGPort ASetupHoldPort BSetupHoldVERILOGTEXT DATAJAVA CLASS01/13/19 6IPCHINOOK - Modal ProcessesConcurrent Interacting modules: Ports, Handlers and modesPorts: Logical communication contact points for inter-process comm.Mode: State of a process, maps inputs to handlersHandlers: Code with run to completion semanticsDispatch message to output portsVote for activation-deactivation of modesMODALPROCESSMODALPROCESSMESSAGESIO PORTHANDLERSMODALPROCESS01/13/19 7Control Composition - Wrist WatchWATCHSTOPWATCHALARMSHOWNSHOWNSHOWNWATCH-UISTOPWATCH-UIALARM-UIWSSSASseqLoopACTModal ProcessModeAbstract Control Types (ACTs)Control co-ordination between componentsEstablish automatically maintained relationships between modes.01/13/19 8Mode Manager SynthesisCoordinating between processesPart of run-time system managing control communication according to ACTsHandles state maintenance taskCentralized or distributed mode managerDepends on target architectureUni-processor or Multi-processorCentralized mode managerExecuted on a uni-processorProcesses run mode-synchronouslyProcesses blocked, No handlers run till mode changes are resolved01/13/19 9Core ImplementationSynopsys DesignWare FlowRTL CodingIn adherence to the Re-use Methodology ManualUnit-level verificationSmall “throw away” test bench for exhaustive unit test prior to integration with top-level IP-blockCode coverage analysisLine CoverageToggle CoverageCondition CoverageIntegration and Verification of core01/13/19 10ModelsA representation of a IP-block used in a particular step of the design or verification flowBus Functional ModelSimulation model used to verify interfaces around coreFull Functional ModelSimulation model representing the full functionality of the coreInstruction Set Architecture ModelArchitecture level model for testing the architecture specific software for a processor core01/13/19 11Communication SynthesisAbstract communication protocols on targetAbstract SpecificationOutput Port: Blocking style, deadline constraintInput Port: Queue size, overflow behaviorMulti-hop deadline distributionHop-processes: Route messagesDistribute deadline along message pathPartitioning takes global view by accounting all bus traffic in systemBus protocol attribute synthesisMessage Ids, Processor Ids, prioritiesDevice driver synthesis01/13/19 12Communication SynthesisProducerProcessOutPortDeviceDriverComm.ChipComm.ChipDeviceDriverMessageRouterInportConsumerProcess01/13/19 13Interface SynthesisProblemGiven two communicating design actors exchanging data, and a description of the two protocols that each one of them uses to transfer the data, determine an interface so that data transfers are consistent with both protocols.01/13/19 14Protocol specificationProtocol : legal sequences of values that may appear on the ports from the onset to the end of the data transferSymbol : a tuple composed of the values on the portsProtocol is simply a set of strings of symbolsThe GoalTo obtain a FSM that when placed between the two modules implementing the specified protocols would make the communication possible01/13/19 15Protocol specification exampleType byte bit[7:0]Type yow { byte a; byte b}Protocol serial of type yow {Master bit start, byte bus;Term null() { 0, - }Term one(byte b) { 1, b }Term two(byte b) { 0, b}Serial(yow y) { null()*, one(y.a), two(y.b) }}Protocol handshk of type yow {master bit trigger, byte bus;term wait(bit t){ t, - }term get(bit t, byte b) { t, b }handshk(yow y) { wait(0)*,get(1,y.a)+,get(0,y.b)+ }}01/13/19 16Synthesis Algorithm01/13/19 17Simulations and VerificationsSimulationsAble to simulate at each design abstract levelsCo-simulationVerificationFunctionality tests to verify the basic operation of the IP and compliance to any standards Deep corner cases to verify the correct functionality of the IP under unusual conditionsRandom testing Silicon prototyping01/13/19 18ConclusionIP component selection and matchingStandards to promote IP reuseVSIA – Virtual Socket Interface AllianceRetargetability through communication and interface synthesisComprehensive hardware/software co-synthesis frameworkEfficient simulation techniques let designers validate their design at different stages of synthesis01/13/19 19ReferencesZhang, T.; Benini, L.; De Micheli, G. Component selection and matching for IP-based design Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings , 2001 Page(s): 40 –46Kucukcakar, K. Analysis of emerging core-based design lifecycle Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on , 1998 Page(s): 445 –449Pai Chou; Ortega, R.; Hines, K.;