ReferencesTypes of Yield-Related ProblemsAn Integrated Circuit (IC) Yield TreeParticles, Defects, and YieldSome IC Yield TerminologyManufacturing Process Flow from the Perspective of Yield Monitoring and ControlStatistical Basis for Yield ModelingReview – Binomial DistributionReview – Poisson DistributionExample: Via YieldBinomial vs. Poisson DistributionDefect (Spatial) Yield ModelingSpatial DefectsPoisson Defect Yield ModelMurphy Yield ModelMurphy Yield ModelMurphy Yield Model, p. 2Seeds Yield ModelComparison of Defect Density ModelsNegative Binomial ModelSpatial DefectsNegative Binomial Model, p. 2How About Size of Defects?Defect Size DistributionCritical AreaMeasurement & Defect Size DistributionHow Measure Defect Size Distribution?Critical AreaCritical Area ExtractionPutting Critical Area and Defect Size Distribution TogetherGlobal Yield LossChip YieldChip YieldCharacterization Vehicles (Test Chips)SummaryMIT OpenCourseWare ____________http://ocw.mit.edu 2.830J / 6.780J / ESD.63J Control of Manufacturing Processes (SMA 6303)Spring 2008For information about citing these materials or our Terms of Use, visit: ________________http://ocw.mit.edu/terms.2.830J/6.780J/ESD.63J 1ManufacturingControl of Manufacturing ProcessesSubject 2.830/6.780/ESD.63Spring 2008Lecture #10Yield ModelingMarch 11, 20082.830J/6.780J/ESD.63J 2ManufacturingReferences• G. May and C. Spanos, Fundamentals of Semiconductor Manufacturing and Process Control, Chapter 5: Yield Modeling (Wiley 2006). • D. J. Ciplickas, X. Li, and A. J. Strojwas, “Predictive Yield Modeling of VLSIC’s,” International Workshop on Statistical Metrology, June 2000.• C. H. Stapper and R. J. Rosner, “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation,” IEEE Trans. on Semicond. Manuf., Vol. 8, No. 2, May 1995.2.830J/6.780J/ESD.63J 3ManufacturingTypes of Yield-Related Problems• Parametric failures– deviations in control (e.g. line width) result in functional failures or quality-loss performance degradation • Random failures– uncorrelated random failure in some element– example: individual via failures• Area dependent failures– failures related to the area of opportunity for failure– example: “killer defect” particles2.830J/6.780J/ESD.63J 4ManufacturingAn Integrated Circuit (IC) Yield TreeImage removed due to copyright restrictions. Please see Fig. 1 in Ciplickas, Dennis J., et al. “Predictive Yield Modeling of VLSIC’s.” IEEE 5thInternational Workshop on Statistical Metrology (2000): 28-37.2.830J/6.780J/ESD.63J 5ManufacturingParticles, Defects, and Yield• Particles are foreign matter on the surface of or embedded within the wafer• A defect is any artifact that might destroy functionality of the circuit (particles are one type of defect)• Functional yield can be reduced by defects– open circuits– short circuits– impact device operation such that function fails Image removed due to copyright restrictions. Please see Fig. 5.2 in May, Gary S., and J. Costas Spanos. Fundamentals of Semiconductor Manufacturing and Process Control. Hoboken, NJ: Wiley-Interscience, 2006.2.830J/6.780J/ESD.63J 6ManufacturingSome IC Yield Terminology• Wafer yield: the percentage of wafers that make it to final probing• Probe testing yield: the percentage of wafers that make it through the probe testing steps • (Functional) die yield: the percentage of chips that make it through a functional electrical testing step (i.e. binary yes/no decision on function)• Parametric (die) yield: the percentage of chips meeting performance specifications (e.g. speed)May & Spanos7Manufacturing Process Flow from the Perspective of Yield Monitoring and ControlMay & SpanosImage removed due to copyright restrictions. Please see Fig. 5.1 in May, Gary S., and J. Costas Spanos. Fundamentals of Semiconductor Manufacturing and Process Control. Hoboken, NJ: Wiley-Interscience, 2006.2.830J/6.780J/ESD.63J 8ManufacturingStatistical Basis for Yield Modeling• The probabilities of discrete failures are generally not Gaussian– Basis in binomial and Poisson statistics• Failure probabilities can be spatial in nature– Opportunities for failure depend on areas2.830J/6.780J/ESD.63J 9ManufacturingReview – Binomial Distribution• Repeated random Bernoulli trials– n is the number of trials– p is the probability of “success” on any one trial– x is the number of successes in n trials• Yield application– probability of x good chips on a wafer with n chips, given probability any given chip is good2.830J/6.780J/ESD.63J 10ManufacturingReview – Poisson Distribution• Poisson is a good approximation to Binomial when nis large and p is small (< 0.1)• Example applications:– # misprints on page(s) of a book– # transistors which fail on first day of operation• Mean:• Variance:2.830J/6.780J/ESD.63J 11ManufacturingExample: Via Yield• Chips have multiple wiring layers with vias between layers– Very small failure probability pvfor any one via.– Millions of vias in each layer on each chip, i.e. n is large.• Statistical Model?– Could use a binomial distribution to find the probability there will be some number x of via failures on the chip– Alternatively, can use a failure rate (or average number of via failures) λv' npvfor vias on a layer. Now the probability of x via failures on some chip is approximated by a Poisson distribution:– Assuming that all vias must work correctly for the chip to work, (i.e. x = 0), what is the probability that the chip is good?2.830J/6.780J/ESD.63J 12ManufacturingBinomial vs. Poisson Distribution• Comparison between approximations of the binomial and Poisson distributions:2.830J/6.780J/ESD.63J 13Manufacturing• D0– average number of defects per unit area• A0– the critical area of the system (the area in which a defect occurring has a high likelihood of causing a fault)Defect (Spatial) Yield ModelingMay & Spanos2.830J/6.780J/ESD.63J 14ManufacturingSpatial Defects• Random distribution• Spatially uncorrelated• Each defect “kills” one chip2.830J/6.780J/ESD.63J 15ManufacturingEmpirical Result: Exponential Dependence of Yield on Chip AreaImage removed due to copyright restrictions. Please see Fig. 1 in Stapper, Charles H., and J. Raymond Rosner. “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation.” IEEE Transactions on Semiconductor Manufacturing 8 (May 1995): 95-102.2.830J/6.780J/ESD.63J