UE EE 254 - EE 254 In class exercise

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EE254 In class exercise Star Date: 1202011 Redraw the following circuit using only NAND gates. You may use NAND gates with more than 2 inputs. Minimize the logic and draw circuit diagram for the function in the K-map below. Use only 2-input AND, 2-input OR, and NOT gates. X’s are don’t cares. CD f 00 01 11 10 00 0 X 0 1 AB 01 0 X 1 0 11 0 1 X 0 10 1 0 0 XDesign a combinational logic circuit described below with four inputs A, B, S0, S1 and output Y0. When S0 = “0” and S1 = “0”, Y0 = 1 if A ≠ B. When S0 = “0” and S1 = “1”, Y0 = “don’t care”. When S0 = “1” and S1 = “0”, Y0 = 1 if A > B. When S0 = “1” and S1 = “1”, Y0 = 1 if A = B. Complete the truth table and the K-Map below and construct the logic circuit using “AND’s”, “OR’s”, and “NOTS”. You may use gates with more than two inputs. S0S1 Y0 00 01 11 10 00 AB 01 11 10 A B S0 S1 Y0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1


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UE EE 254 - EE 254 In class exercise

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