Tutorial on High-Level Synthesis Michael C. McFarland, SJ Alice C. Parker Boston College University of Southern California Chestnut Hill, MA 02167 Los Angeles, CA 90007 Raul Carnposano IBM T.J. Watson Research Center Yorktown Heights, NY Abstract. High-level synthesis takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. In this tutorial we will examine the high-level synthesis task, showing how it can be decomposed into a number of distinct but not independenl. sub- tasks. Then we will present the techniques that have been developed for solving those subtasks. Finally, we will note those areas related to high-level synthesis that are still open problems. 1. Introduction 1.1 What is High-Level Synthesis? The synthesis task is to take a specification of the behavior required of a system and a set of constraints and goals to be satisfied, and to fmd a structure that implements the behavior while satisfying the goals and constraints. By behavior we mean the way the system or its components interact with their environment, i.e., the mapping from inputs to outputs. Structure refers to the set of interconnected components that make up the system - something like a netlist. Usually there are many different structums that can be used to realize a given behavior. One of the tasks of synthesis is to tlnd the structure that best meets the constraints, such as limi- tations on cycle time. area or power, while minimizing other costs. For example, the goal might be to minimize area while achieving a certain minimum processing rate. Synthesis can take place at various levels of abstraction because designs can be described at various levels of detail. The type of synthesis we will focus on in this tutorial begins with a behavioral specification at what is often called the algorithmic level. The pri- mary data types at this level are integers and/or bit strings and arrays, rather than boolean variables. The input specification gives the required mappings from sequences of inputs to sequences of outputs. It should constrain the internal structure of the system to be designed as little as possible. From that input specification, the synthesis system produces a description of a register-rran#er level structure that realizes the specified behavior. This sbuctum includes a data path, that is, a network of registers, functional units, multiplexem and buses, as well as hardware to control the data transfers in that network. If the control is not integrated into the datapath -and it usually is not - the synthesis system must also produce the specification of a fmite state machine that drives the datapaths so as to produce the required behavior. The conno specification could be in terms of microcode, a PLA profile or ran- dom logic. High-level synthesis as we define it must be distinguished from other types of synthesis, which operate at different levels of the design hierarchy. For example, high-level synthesis is noL to be confused with logic synthesis, where the system is specified in terms of logic equations, which must be optimized and mapped into a given technology. Logic synthesis might in fact be used on a design after high-level synthesis has been done, since it pmsup- poses the sorts of decisions that high-level synthesis makes. At the other end of the spectrum, there is some promising work under way on system level synthesis, for example on partitioning an algo- rithm into multiple processes that can run in parallel or be pipe- lined. However, this. work is still in its preliminary stages: and we will not report on it hem. 1.2 Why Study High Level Synthesis? In recent years there has been a trend toward automating synthesis at higher and higher levels of the design hierarchy. Logic syn- thesis is gaining acceptance in industry, and there has been consid- erable interest shown in synthesis at higher levels. There am a number of masons for this: . Shorter design cycle. If mom of the design process is automated, a company can get a design out the door faster, and thus have a better chance of hitting the market window for that design. Furthermore, since much of the cost of the chip is in design development, automating mom of that process can lower the cost significantly. - Fewer Errors. If the synthesis process can be verified to be correct - by no means a trivial task - there is a greater assurance that the final design will correspond to the initial specification. This will mean fewer errors and less debugging time for new chips. . The ability to search the design space. A good synthesis sys- tem can produce several designs for the same specification in a reasonable amount of time. This allows the developer to explore different trade-offs between c0st, speed, power and so on, or to take an existing design and produce a functionally equivalent one that is faster or less expensive. - The design process is self-documenting. An automated sys- tem can keep track of what design decisions were made and why, and what the effect of those decisions was. . Availability of IC technology to more people. As more design expertise is moved into the synthesis system, it becomes easier for a non-expert to produce a chip that meets a given set of specifications. We expect this trend toward higher levels of synthesis to continue. Already there are a number of research groups working on high- level synthesis, and a great deal of progress has been made in finding good techniques for optimization and for exploring design trade-offs. These techniques are.very important because decisions made at the algorithmic level tend to have a much greater impact on the design than those at lower levels. Them is now a sizable body of knowledge on high-level synthesis, although for the most part it has not yet been systematized. In the remainder of this paper, we will describe what the problems are in high-level synthesis, and what techniques have been developed to solve them. To that end, Section 2 will describe the various tasks involved in developing a register-transfer level structure from an algorithmic level
View Full Document
Unlocking...