PSoC 3 PSoC 5 102 System Resources Introduction to PSoC 3 PSoC 5 Workshop Rev H 1 Section Objectives Objectives you will be able to Understand the system block diagram of PSoC 3 PSoC 5 devices Understand and use the PSoC 3 PSoC 5 System Resources including Power system Programming debugging Configuration and boot process Resets Clocking Memory mapping DMA and PHUB I O Interrupts Introduction to PSoC 3 PSoC 5 Workshop Rev H 2 System Block Diagram Introduction to PSoC 3 PSoC 5 Workshop Rev H 3 Power System and Supplies no boost Standard Power Configuration No boost pump Vdda Vddd Vddio0 1 2 3 Vdda 1 8 5 5V Supply Rules Usage Vdda Must be highest voltage in system Supplies analog high voltage domain and core regulator Vddd Supplies digital system core regulators Vcca Output of the analog core regulator An external 1 3 uF capacitor to ground is required Vccd Output of the digital core regulator A single external 1 3 uF capacitor to ground is required Both Vccd pins must be tied together on the PCB and share the single 1 3 uF capacitor Vddio0 1 2 3 Independent I O supplies May be any voltage in the range of 1 8V to Vdda Introduction to PSoC 3 PSoC 5 Workshop Rev H 4 Power System with boost Boost Converter Configuration Used to generate up to 5 0V Vout Battery voltage as low as 0 5V Vbat Output voltage and current limit based on input voltage and boost ratio 75 mA max current 0 5 0 8V Vbat provides max of 1 95V Vout Schottky diode required when Vout is 3 6V Synchronous rectification maximizes efficiency Boost may be used to power external circuits independent of PSoC Vdda and Vddd voltage If boost not used Vssb Vbat and Vboost must be tied to ground Ind left floating Introduction to PSoC 3 PSoC 5 Workshop Rev H 5 Programming Debug Interfaces JTAG Legacy 4 wire Interface Supports all programming and debug features Serial Wire Debug SWD Standard 2 wire interface for all CY tools and kits Supports all programming and debug features with same performance of JTAG Default debug interface in PSoC Creator Serial Wire Viewer SWV Supports 32 mailboxes for application printf type debug Uses only 1 pin Introduction to PSoC 3 PSoC 5 Workshop Rev H 6 Programming and General Features Standard Flash Operations Erase all Erase block 256 blocks per device independent of Flash size Program block Set block security 4 levels same as PSoC 1 Unprotected No protection Factory Upgrade Prevents external read Field Upgrade Prevents external read and write Full Protection Prevents external read and write as well as internal write General Features available through JTAG SWD IO boundary scan through JTAG interface Enable Disable JTAG and SWD interfaces On Chip Debug features enabled disabled by firmware Introduction to PSoC 3 PSoC 5 Workshop Rev H 7 On Chip Debug OCD Debug Features 1 PC Memory Dependant Trace Details PSoC 3 4k on chip instruction trace included in all devices Trace memory may be used as system memory PSoC 5 Select devices include ARM External 5 wire Trace Macrocell supporting ETM ITM and DWT Introduction to PSoC 3 PSoC 5 Workshop Rev H 8 Reset Sources PPOR Power On Reset XRES External reset pin PRES Under voltage on external supplies Vddd Vdda PRES Under voltage on internal supplies Vccd Vcca AHVI Over voltage on Vdda HRES Hibernate mode under voltage detect SRES User software and or hardware generated reset WRES Watchdog reset JTAG or SWD interface generates reset Introduction to PSoC 3 PSoC 5 Workshop Rev H 9 Clocking Sources Internal Main Oscillator 3 67 MHz 1 at 3 MHz 5 at 67 MHz PLL output 12 67 MHz can not use 32 kHz crystal External clock crystal input 4 33 MHz External clock oscillator inputs 0 33 MHz Clock doubler output 12 48 MHz Internal Low speed oscillator 1 kHz 33 kHz and 100 kHz External 32 kHz crystal input for RTC 3 67 MHz IMO 4 33 MHz ECO 0 33 MHz Ext Osc 32 kHz ECO 1 33 100 kHz ILO PLL Introduction to PSoC 3 PSoC 5 Workshop Rev H 10 Clock Distribution Clock dividers 16 bit dividers 8 clock source inputs 8 digital clock dividers 4 analog clock dividers Provide skew control to reduce digital switching noise 3 67 MHz IMO 4 33 MHz ECO 0 33 MHz Ext Osc 32kHz ECO 1 33 100 kHz ILO PLL 7 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit Bus CPU Divider 16 bit Digital Clock Divider 16 bit 1 CPU divider Digital Clock Divider 16 bit UDBs can be used to create additional digital clocks Digital Clock Divider 16 bit Analog Clock Divider Skew 16 bit Digital Clock Divider 16 bit Analog Clock Divider Skew 16 bit Digital Clock Divider 16 bit Analog Clock Divider Skew 16 bit Digital Clock Divider 16 bit Analog Clock Divider Skew 16 bit Introduction to PSoC 3 PSoC 5 Workshop Rev H 11 System Clock Setup Introduction to PSoC 3 PSoC 5 Workshop Rev H 12 Clock Management Clocks allocated to dividers in clock tree Clocks have software APIs to dynamically change frequency Note Reuse existing clocks to preserve resources Introduction to PSoC 3 PSoC 5 Workshop Rev H 13 8051 Memory Map Internal Data space IDATA 256 Bytes of SRAM Standard 8051 specific SFR registers Access port data registers through SFRs External Data space XDATA 16MB Up to 8 KB of SRAM on lead devices All PSoC peripheral and configuration registers EEPROM Flash External memory Interface EMIF Introduction to PSoC 3 PSoC 5 Workshop Rev H 14 ARM Cortex M3 Memory Map Single 4 GB address space Registers from 8051 map into 0 5 GB peripheral region s bit band region for efficient bit operations Introduction to PSoC 3 PSoC 5 Workshop Rev H 15 External Memory Interface EMIF EMIF Supports Sync SRAM Async SRAM Cellular RAM NOR Flash EMIF Usage PSoC 3 Data only PSoC 5 Data and program 8 or 16 bit data bus 8 16 or 24 bit address bus Max throughput 11 16 MHz depending on configuration details Introduction to PSoC 3 PSoC 5 Workshop Rev H 16 Software Use of Registers 8051 and ARM Cortex M3 Provide same functionality address mapping to all PSoC 3 PSoC 5 registers Use Peripheral Hub PHUB bus Macros hide MCU compiler differences enabling PSoC 3 PSoC 5 portability cytypes h CY GET REG8 addr CY SET REG8 addr value cydevice trm h Contains device register defines 8051 includes SFR registers allowing direct register access Affects portability to PSoC 5 if used PSoC3 8051 h Contains SFR register defines Introduction to PSoC 3 PSoC 5 Workshop Rev H 17 Flash Flash Blocks 256 Blocks in all devices 64 KB flash has 256 byte block size Each block may be set to 1 of 4 protection levels of increasing security Unprotected Allows internal and external reads and