Main PageISSS98Front MatterTable of ContentsSession IndexAuthor IndexConcurrent Error Detection at Architectural LevelC. Bolchini, W. Fornaciari, F. Salice, D. SciutoPolitecnico di Milano, Dip. di Elettronica e Informazione,P.zza L. Da Vinci, 32 – 20133 Milano, ItalyAbstractA methodology for designing systems with concurrent er-ror detection capability is introduced. The proposed ap-proach consists of a functional architecture and a check-ing architecture to verify data computed by the functionalone. The methodology reduces both redundancy and la-tency through hardware resources and data sharing, re-spectively.1. IntroductionCAD-related design methodologies are nowadays themeans for designing embedded systems, in particular thoseadopted in mission-critical environments (e.g. telecom,automotive electronics,...), allowing the adoption of adhoc solutions to ensure properties that are not purely func-tional (e.g., testability, self-checking (SC), ...).Typical application-specific design approaches take fulladvantages from high-level synthesis techniques. Con-forming the design to the requirements of a self-checkingsystem is usually left to a lower abstraction level (logicalor transistor level), by suitably modifying the architecturevia data encoding and constrained specific logic synthesis.Proposal approaches operate through a suitable encodingin the state assignment of FSMs as well as by encoding thedata flowing into the data path supported by a subsequentspecific logic synthesis [1][2][3]. However, these method-ologies suffer of some drawbacks and, furthermore, theyare introduced when most of the synthesis steps have al-ready been carried out, so that the resulting system is notoptimized with respect to the overall functionality of thecircuit.The aim of this work is to shift the handling of the self-checking properties towards the upper levels of the designprocess (high-level) to enhance resource exploitationwhile granting autonomous error detection capability (notrequiring the modification of the functional circuit).The paper, in Section 2, initially introduces the classesof faults we are considering, the target architecture forhigh-level synthesis and the modifications necessary toobtain a self-checking system. Section 3 presents the pro-posed approach, by detailing the design methodology.Two different classes of approaches can be envisioned.The first has the goal of fulfilling both design constraintson time, performance and checking latency, by exploitingthe data dependencies. The second attempts to overcome anot optimal exploitation of the resources by introducing aninterleaving between the computation and the checkingactivities. Other proposals can be found in literature con-cerning similar design methodologies [4][5]. The proposedwork focuses the attention on the optimization of thehardware resources by acting on the global scheduling andresource allocation. The approach presented in [4] opti-mizes the scheduling itself by using a multidirectionalforce-directed scheduling on a region based partitioning ofthe data-flow graph. On the other hand, the proposal pre-sented in [5] aims at providing a semi-concurrent errordetection ability.Section 4 reports some considerations concerning the im-plementation cost. Experimental data concerning a smallexample outlining the potential benefits of the proposedapproach are also included. Section 5 draws some conclu-sions and outlines future investigations.2. Preliminaries2.1. Architectural ModelThe target is the multiplexer-based architecture (Fig. 1).RRRFUFURMUX MUXMUXMUX MUXMUXFig 1. The target synthesis architecture.Multiplexer-based architectures are composed of func-tional units (FU) and registers; in this organization, eachdata transfer between FUs and registers occurs throughmultiplexers and each value produced by a functional unitis stored into a register through multiplexers [6].2.2 Self-checking ArchitectureThe self-checking architecture is mainly composed of twoelements: the functional architecture and the checkingarchitecture. A single control unit is used. The functionalpart is the one designed without any self-checking capa-bilities provided by the checking section.CheckingArchitectureControlUnitFunctionalArchitectureControllablecheckersoutputs f ginputstestFig 2. The architecture of the self-checking system.2.3 Fault Model and Faults EquivalenceThe fault model refers to the stuck-at fault (s-a-0, s-a-1),widely adopted at the register transfer level, and, withrespect to the present architecture, covers the followingclasses:• faults affecting any component of the data path. Notethat multiple faults inside each component can be dealtwith provided they generate an observable error;• input and output lines of any component;• the control unit, thus generating erroneous control con-figurations for the data path. Moreover, multiple faults affecting different componentsof the data path can be detected if they cause differentlyobservable errors. 3. Checking Architecture Design As depicted in Fig. 2, the verification of the correct be-havior of the functional architecture can be performed bymeans of a checking unit. to compare intermediate or finalresults at some checkpoints. Checkpoint positioning de-pends on the specific characteristics of the application andon the design goals, such as the level of observability ofthe results, cost, and state restoring in case of fault tolerantsystems. In the following we deal mainly with datapathsynthesis, since it constitutes the most relevant factor in-fluencing gate count for our target applications. Threeproposals are presented; the starting point for all of them isa datapath optimized for cost or speed (allocation andbinding have already been performed). The first solutionguarantees a null latency and the goal is area minimizationwhile the other approaches are tailored for applicationswhere silicon cost is the key factor. 1. Data Dependency Driven Methods This first class of methods allows the realization of achecking architecture maintaining the same dependenciesamong data. Two approaches are available and differ interms of objectives although both aim at improving re-source exploitation with scheduling and allocation strate-gies using the entire set of available resources in a givenset of control steps (Csteps). The initial system has achecking architecture equal to the functional one, afternormal scheduling and allocation. a) Time Constrained - Force Directed Based Schedulingfor