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xPilot A Platform Based System Level Synthesis for Reconfigurable SOCs Prof Jason Cong cong cs ucla edu UCLA Computer Science Department Motivation Design complexity is outgrowing the traditional RTL method even in current CMOS technologies Nanotechnology will enable 10 100x increase in device density and degree of integration Need to enable higher level of design abstraction Start from behavior descriptions e g C or SystemC Use and or re use more complex functional unit e g processor cores instead of standard cells ESL Tools A Lot of Interests xPilot Platform Based Synthesis System Platform Description Constraints SystemC C xPilot xPilot Front End Profiling SSDM System Level Synthesis Data Model Processor Architecture Synthesis Processor Cores Executables Interface Synthesis Drivers Glue Logic Analysis Mapping Behavioral Synthesis Custom Logic FPSoC Uniqueness of xPilot Platform based synthesis and optimization Communication centric synthesis with interconnect optimization xPilot Behavioral to RTL Synthesis Flow Behavioral spec in C SystemC Platform description Frontend Frontend compiler compiler FPGAs ASICs FPGAs ASICs Loop unrolling shifting Strength reduction Tree height reduction Bitwidth analysis Memory analysis Core synthesis optimizations Scheduling Resource binding e g functional unit binding register port binding SSDM SSDM RTL constraints Presynthesis optimizations Arch generation RTL constraints generation Verilog VHDL SystemC FPGAs Altera Xilinx ASICs Magma Synopsys System Level Exploration Using xPilot for Heterogeneous MPSoC Platforms Heterogeneous MPSoCs exploration Processors Heterogeneous vs homogeneous General purpose vs application specific On chip communication architecture OCA Bus e g AMBA CoreConnect packet switching network e g Alpha 21364 Memory hierarchy P P tasks OS Driver Network Interface Network Interface IP P Network Interface Network Interface P P tasks OS Driver Network Interface Network Interface FPGA P Network Interface Network



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