Contains material © Digilent, Inc. 8 pages Lab #7 Getting to Know Combinational Circuits through Verilog Revised 2_28_11 Combinational logic circuits are circuits that are only dependent on the current state of the inputs. There is no relationship between what happened in the past to the present output. As we grow in our capabilities and knowledge of digital circuits, using building blocks allows us to use a hierarchical approach to design. The combinational building blocks we will be looking at in the lab are a) Multiplexers b) Decoders After completing this module, you should… - Synthesize multiplexers, decoders, and using continuous assignments statements and module instantiation. - Write Verilog code for the circuits. This module requires: - The Digital BaSYS boardLab #7 Getting to Know Combinational Building Blocks through Verilog Contains material © Digilent, Inc. 2 Background Multiplexer (mux) and Demultiplexer (demux or decoder) In electronics, a multiplexer or mux is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. On the other end, a demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-output-lines, which is connected to the single input. A multiplexer is often used with a complementary demultiplexer on the receiving end. FIGURE 1 MULTIPLEXER FIGURE 2 DEMULTIPLEXER An electronic multiplexer can be considered as a multiple-input, single-output switch, and a demultiplexer as a single-input, multiple-output switch. The schematic on the right shows a 2-to-1 multiplexer on the left and an equivalent switch on the right. The ‘sel’ wire connects the desired input to the output. Consider the cell phone which uses wireless communication. A transmission station handles a lot of simultaneous calls from many users. A simple and widely used method is time division multiple access (TDMA) which allows many users to share common wireless channel by using assigning time slots on each users. In rapid succession, the voice data is packaged and transmitted on one’s time period, which is fast enough for users not to perceive the time interval between the voice packets. The aggregated voice data are transmitted through reliable and fast medium such as optic fiber to other parties. The transmission station which received voice data distributed the signals to the users by using demultiplexer. It should be noted that to make sure each end caller and receiver must match correctly. We call this synchronization, and ‘sel’ signal on the diagram does this job. Another example is internet, which is shown on following figure.Lab #7 Getting to Know Combinational Building Blocks through Verilog Contains material © Digilent, Inc. 3 The most important reason why we use mux and demux is to save cost. The figure above describes well. The cost of implementing separate channels for each data source is more expensive than the cost and inconvenience of providing the multiplexing/demultiplexing functions. In a physical analogy, consider the merging behavior of commuters crossing a narrow bridge; vehicles will take turns using the few available lanes. Upon reaching the end of the bridge they will separate into separate routes to their destinations. In our previous lab, scrolling student ID also uses multiplexer and demultiplexer. Light blue box represents 4-1 quad mux where quad mean 4 bits or 1 Hex value are processed. Red box represent 2-4 demux because select signal has 2 bit binary and the output is 4 bit SSD control signal, AN[3:0]. Depending on the SELECT signal, data_selector choose one hex value to pass it the converter. Simultaneously, SSD_selector chooses one SSD to show the hex value by using the SELECT signal. Yellow arrows show the flow of the data at the same time. The SELECT signal is used for synchronization purpose between two major modules, data_selector and SSD_selector. In this lab, we will learn how the detail of multiplexer and demultiplexer which are fundamental parts of combinational circuits which only consider current signal. Next lab, we will learn sequential circuits which care previous outputs. Data Selector (4-1 Quad Mux) 9 4 7 D 0 … 1 2 3 Ctr2Sel CLK CLR SSDSelector 2-4 Demux Hex7Segment A_TO_G [6:0] AN [3] Scrolling a student ID on the 7-segment display x7segment HEX SELECT[1:0] Shift array SELECT[1:0] AN [2] AN [1] AN [0]Lab #7 Getting to Know Combinational Building Blocks through Verilog Contains material © Digilent, Inc. 4 Verilog: Continuous Assignment We’ve been using gate primitive representation for the structural code. There is another type of writing the structural code, which is continuous Assignment. Here are some characteristics of continuous assignment. - They can be used for modeling combinational logic. - They are outside the procedural blocks (always statement and initial blocks). - The left-hand side of a continuous assignment must be net (wire) data type. - They may have a delay specified. (We will use this property next lab) Here is an example of a continuous assignment statement, also called a net-assignment statement comparing with gate primitives representation. Continuous Assignment Gate Primitives assign Z = (~S & A) | (S & B); and(S_notA, ~S, A); and(SB, S, B); or(Z, S_notA, SB); Where ~ is not operator and & is and operator. This is very similar to the SOP or POS equations written for each output, and it is simpler than gate primitive representation. From now on, we will use one of both methods as needed. Below is a table of Verilog operators to be used for the net-assignment statements. Operator (function) ~ ( NOT) | (OR) ~^ (XNOR) & (AND) ^ (XOR) We will use continuous assignment statements for this lab.Lab #7 Getting to Know Combinational Building Blocks through Verilog Contains material © Digilent, Inc. 5 Combinational Circuits Mux (2 to 1) Mulitplexers are data selectors. They allow one of n-input values to be passed to the output. The truth table for a 2-to-1 multiplexer is shown below along with the corresponding equation, two-level AND/OR circuit, and the 2:1 mux symbol. FIGURE 3 MUX 2-TO-1 (A) GRAPHICAL SYMBOL (B) CIRCUIT S A B Z 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1111 0 0 0 0 1 1 1 0 0 1 1 1 FIGURE 4 TRUTH TABLE (FULL AND ABBREVIATED