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PIC18F Programming Model and Its Instruction Set Updated: 2/2/2014 Chapter 3Access RAM Data Memory Organization PIC16F8F2520/4520 Register File Map 000h 07Fh 256 Bytes Bank 0 GPR Bank 1 GPR Bank 2 GPR Bank 13 GPR Bank 14 GPR Bank 15 GPR Access SFR Access RAM Access SFR 080h 0FFh 100h 1FFh 200h 2FFh D00h DFFh E00h EFFh F00h FFFh F7Fh F80h 00h 7Fh 80h FFh Access Bank o Data Memory up to 4k bytes o Divided into 256 byte banks o Half of bank 0 and half of bank 15 form a virtual bank that is accessible no matter which bank is selected Remember:Register File Concept Data Bus d Decoded Instruction from Program Memory: Arithmetic/Logic Function to be Performed Result Destination Address of Second Source Operand o Register File Concept: All of data memory is part of the register file, so any location in data memory may be operated on directly o All peripherals are mapped into data memory as a series of registers o Orthogonal Instruction Set: ALL instructions can operate on ANY data memory location w f w f ALU WREG Data Memory (Register File) 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h Opcode d a Address 0 1 a-bit a = 0 access bank a = 1 use BSRPIC18F Programming Model (1 of 2) o The representation of the internal architecture of a microprocessor, necessary to write assembly language programs n Programming Model o Two Groups of Registers in PIC16 8-bit Programming Model n ALU Arithmetic Logic Unit (ALU) n Special Function Registers (SFRs) from data memoryPIC18F Programming Model (2 of 2) Register Size: 16 Register Size: 8Registers o WREG n 8-bit Working Register (equivalent to an accumulator) n Used for arithmetic and logic operations o BSR: Bank Select Register (0 to F) n 4-bit Register o Only low-order four bits are used to provide MSB four bits of a12-bit address of data memory.1 0 0 0 0 0 1 Register Direct Addressing 4-bits from BSR Register 8-bits Encoded in Instruction BSR (Bank Select Register) ʻfʼ Operand 0 0 0 1 0 0x282 12-bit Effective Address (Use this when coding) FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 00 Bank0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 01 02 03 7D 7E 7F 80 81 82 FC FD FE FF Bank1 Bank2 FF FF FF FF FF FF FF FF FF FF FF FF Bank13 Bank14 Bank15 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ʻaʼ Bit from Instruction 11 0 0 0 0 0 1 Register Direct Addressing 4-bits from BSR Register 8-bits Encoded in Instruction BSR ʻfʼ Operand 0 0x82 12-bit Effective Address (Use this when coding) 00 Bank0 01 02 03 7D 7E 7F 80 81 82 FC FD FE FF Bank1 Bank2 Bank13 Bank14 Bank15 ʻaʼ Bit from Instruction 0STATUS: Flag Register Flags in Status Register o C (Carry/Borrow Flag): set when an addition generates a carry and a subtraction generates a borrow o DC (Digit Carry Flag): also called Half Carry flag; set when carry generated from Bit3 to Bit4 in an arithmetic operation n Used for BCD representation o Z (Zero Flag): set when result of an operation is zero o OV (Overflow Flag): set when result of an operation of signed numbers goes beyond seven bits – if the results fall outside 127 (0x7F) and -128 (0x80) o N (Negative Flag): set when bit B7 is one of the result of an arithmetic /logic operationExample: PIC18 Visual Interpreter ADD: 9F and 52. Which flags will be set? ADD: 9F and 72. Which flags will be set? N=1 OV=0 Z=0 C=0 1001 1111 0101 0010 ------------- 1111 0001 =F1 N=1 OV=0 Z=0 C=1 1001 1111 0111 0010 ------------- 0001 0001 =F1 0111 0010 0001 0001 ------------- 0000 0011 =02Examples Clearing STATUS Register L-WàW L-WàW Note: 0x01-0x80à81/ Note that this can be interpreted as 1-(-128)=+129à Overflow!File Select Registers (FSR) o Three registers holding 12-bit address of data registers n FSR0, FSR1, and FSR2 o File Select Registers composed of two 8-bit registers (FSRH and FSRL) o Used as pointers for data registers for indirect addressing n Associated with index (INDF) registers Find FSR0-FSR2 in Special Function Register – page 64 What are the File addresses for each? / How many INDF do you find?File Select Registers (FSR) – Indirect Addressing o The main application of FSR is Indirect Addressing n FSRs will be pointing at the address of the data file and they can be incremented n This is much easier than using direct addressing 1A 2D 3D 4D 0x1F34 FSR0=0x1F34 Data MemoryDirect and Indirect Addressing http://www.mikroe.com/chapters/view/3/chapter-2-core-sfrs/Stack and Table Pointers o Table Pointer n 21-bit register used as a memory pointer to copy bytes between program memory and data registers o Stack Pointer (SP) n Stack is a group of 31 word-size registers used for temporary storage of memory address during execution n Requires 5-bit address n Saved in STKPTR in SFR n Used primarily for saving PC for next program address prior to entering subroutine Examine Table 3-1 – Page 64FSR Don’t confuse SFRs and FSRs (file Select Registers)Program Counter 0 1 2 3 4 5 6 7 8 9 10 11 12 PCL PCH Program Counter o 21-bit PC can access up to 221 = 2MB (1MWord) o 22nd bit used to access configuration memory at program time or via table reads & writes o Contains address of NEXT instruction (pipelining) o Lower byte accessible in data memory as PCL o Upper bytes indirectly accessible via PCLATH/PCLATU o Bit 0 of PC is always ʻ0ʼ except when reading or writing program memory via table read/write mechanism 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 14 15 16 17 18 19 20 21 PCU 21-bit register functions as a pointer to program memory during program execution PCLATH PCLATL21-Bit PC Example & Program Memory Leave spaceProgram Memory is Byte Addressable o Low byte has even address, high byte has odd address o Addresses of instructions are always even o 16-bit wide program memory is byte addressable o All program instructions will start at an even address o So if we are jumping 4 instructions ahead, we are actually jumping 8-bytes (or 8 word addresses) ahead 16-bit Program Memory 0x000000 0x000002 0x000004 0x000006 0x000008 0x00000A 0x00000C 0x00000E 0x000001 0x000003 0x000005 0x000007 0x000009 0x00000B 0x00000D 0x00000F High Byte Address Low Byte Address Word Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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