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SJSU EE 166 - Class 13

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EE-166 Class 13 1EE-166 Class 13David W. ParentSJSUEE-166 Class 13 2Switch Model of MOSFETS• We can think of PMOSFETs in the following manner:– When VIN=5 the source and drain are not connected– When VIN=0 the source and drain are connected • We can think of NMOSFETs in the following manner:– When VIN=5 the source and drain are connected– When VIN=0 the source and drain are not connectedEE-166 Class 13 3PMOSFETs• Consider the following circuit:CLOADVDDVINCLOADVDDVIN•When the switchis closed, Cloadis charged up toVDD.•There is no pathto discharge Cload.EE-166 Class 13 4NMOSFETs• Consider the following circuit:•When the switchis closed, Cloadis discharged downto GND.•There is no pathto charge Cload.CLOADVINCLOADVINEE-166 Class 13 5Example• Determine the transfer function of the following circuit:VDDVAVBVCVDCLOADVOUTVA VB VC VD VOUT 0 0 0 0 0 0 0 5 0 0 5 0 0 0 5 5 0 5 0 0 0 5 0 5 0 5 5 0 0 5 5 5 5 0 0 0 5 0 0 5 5 0 5 0 5 0 5 5 5 5 0 0 5 5 0 5 5 5 5 0 5 5 5 5EE-166 Class 13 6Stick Diagram• We need a simpler way to represent our layouts so we can “rough in” where everything is going to go.• Stick diagrams are our solution. They show:– NWELL, Poly, Active, Metal layers, and connections.– You do not even need color markers!EE-166 Class 13 7Inverter RepresentationNWELLACTIVEACTIVEPOLYGNDVDDEE-166 Class 13 8Random FunctionalityACTIVEPOLYGNDVDDNWELLACTIVEEE-166 Class 13 9Additional Uses for the Stick Diagram• Clock Routing/Trees• Block Placement• VDD Routing• VSS (GND) Routing• Pad PlacementEE-166 Class 13 10Layout• Layout is the process of drawing how the circuit will look underneath a microscope.– Each layer represents very specific instructions to the fabrication house.– You need to know the basic CMOS fabrication steps to understand what each layer doesEE-166 Class 13 11CMOS Inverter Schematic and Layout11EE-166 Class 13 12CMOS Inverter Layout and Cross SectionP+N+ N+N+P+A AGND Y VDDPWELLNWELLP+Gate NMOS Gate PMOSSSDDAYEE-166 Class 13 13Design Rule Checking• Every layer has its own rules with respect to minimum size, spacing and overlap to other layers. This is done to insure that all the devices work even after variances of the real world creep in.• Running DRC, check for violations in your layout file.EE-166 Class 13 14Design Rule Checkinghttp://www.mosis.com/Technical/Designrules/scmos/scmos-main.htmlEE-166 Class 13 15Alignment Errors• A- No Errors• B- Worst Case x misalignment• C- Worst Case y misalignment• D- Worst case x and yABC DyxWe need to have aminimum overlap of themetal to contact to take into account the inherent errors in alignment.EE-166 Class 13 16Design Rules for a Process• For high yields we need to have a process that can withstand large process variations– ½ of our smallest feature size is equal to λ.λis equal to 45nm μmMinimum contact width 2λMinimum Diffused (N+)width 2λMinimum GateOxide Length(N+) width 4λMinimum Metal width 2λMinimum Diffused/contact overlap 1λMinimum Metal/contact overlap 2λEE-166 Class 13 17Layout vs. Schematic• Once your circuit is laid out, and passes DRC, you need to extract a circuit from the picture you drew and compare it to the schematic you designed and verified (LVS)• After a successful LVS you need to re-run your simulation to make sure you are still within Specification.EE-166 Class 13 18Basic Processing Steps• Grow Silicon Dioxide• Create NWELL regions (Implant)• Etch Active regions and grow gate oxide– VT adjust Implant (NACTIVE=PACTIVE)• Deposit Poly Silicon (POLY1)– Dope, then PatternEE-166 Class 13 19Basic Processing Steps• Implant P+ Source and Drain for PMOS and body contact for NMOS (PSEL)• Implant N+ Source and Drain for NMOS and body contact for PMOS (NSEL)• Create Contact windows (CONT)• Deposit and pattern metal layer (METL1)EE-166 Class 13 20NWELLNote: Channel Stop implants not shown.EE-166 Class 13 21ActiveEE-166 Class 13 22PolyEE-166 Class 13 23N SelectEE-166 Class 13 24P SelectEE-166 Class 13 25Blanket CVD Oxide and Contact (cc)EE-166 Class 13 26Metal 1EE-166 Class 13 27Vias in IC design• In PCB manufacture Vias (Hole between layers go through the whole board.• In IC Design a via connects only two metal


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SJSU EE 166 - Class 13

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