EE 3714 Logic Gates14 Logic GatesThis experiment will introduce AND, OR, NAND, NOR and Exclusive ORlogic gates. You will learn about:¾ Electrical characteristics of logic circuits.¾ Operation of basic gates.¾ The concept of a universal gate.¾ The power of two-level logic.¾ The use of multiple levels to expand gate inputs.EE 3714 Logic Gates2I. PrelabYou must have this information when you ENTER THE LAB.A. Use the TTL Logic Data Book to locate the following information.1. Define tPHL and tPLH.2. Locate the datasheets for the following parts: 74LS08, 74LS00,74LS32, 74LS02, 74LS86.a. Create a table that shows the TYPICAL delay values fortPHL and tPLH for each gate.b. There are more delay values for the 74LS86 than there arefor the other gate types. Why is this? EXPLAIN!3. From the datasheet of the 74LS00:a. What is the minimum input voltage for a logic ‘1’?b. What is the minimum input voltage for a logic ‘0’?c. What is the minimum output voltage for a logic ‘1’?d. What is the minimum output voltage for a logic ‘0’?.e. Compute the difference (C – A), (D-B). Why must this bea positive number? Explain what a “noise margin” is andwhy it is important.B. Prepare truth tables for each of this experiment's logic diagrams.C. Label each of the logic diagrams with pin assignments using theTTL Data Book.In future experiments you will be required to perform prelab assignments similar to thosejust listed. However, the procedures will not be given explicitly in your lab manual.II. Procedure………………………………………………………………………………………………………A. Assemble the circuits in Figure 1 through Figure 5. Verify that eachcircuit operates as expected. Compare your results with those in yourtruthEE 3714 Logic Gates3tables.Figure 2 NANDabzFigure 3 ORFigure 4 NORFigure 1 ANDFigure 5 XORabzabzzababz1231231231233740217408 740074327486B. A universal gate is a logic gate that can be used to create all the basiclogical functions. These two gates are the NAND and the NOR.1. Connect the circuit in Figure 6 and verify that it operates as aninverter.2. Connect the circuit in Figure 7 and verify that it operates as aninverter.3. Connect the circuit in Figure 8 and verify that it operates as an ORgate.xyFigure 6xyFigure 7zFigure 8zab4. Assemble each of the circuits in Figure 9 through Figure 11 anddetermine the equivalent gate represented by eachcircuit.Figure 10 Figure 11Figure 9abzzababzC. All combinational logic functions can be represented in sum-of-products(AND/OR) form and product-of-sums (OR/AND) form. This implies thatall functions can be implemented in two levels of logic provided that ateach level gates have enough inputs. In practice, this may not berealizable due to limitations on fan-in (maximum number of inputs a gatemay have). It should also be noted that AND/OR and OR/AND forms canbe converted to forms that use only the universal gates.1. Assemble the circuits in Figure 12 and Figure 13 and show that the(AND/OR) form is equivalent to the (NAND/NAND) form.EE 3714 Logic Gates4Figure 13abzFigure 12abcdcdz2. Assemble the circuits in Figure 14 and Figure 15 and show that the(OR/AND) form is equivalent to the (NOR/NOR) form.Figure 14Figure 15zabzcdabcdD. Fan-in can be increased using multiple levels of two-input gates1. Connect the circuit in Figure 16 and show that it operates as a three-input AND gate.abczFigure 162. Assemble the circuits in Figure 17 and Figure 18 and determinewhich circuit operates as a three-input NANDgate.Figure 17abzcFigure 18abczlogic`1'E. In logic circuits it is not always obvious that there is a time delay betweenthe time an input changes and the time the output changes. This delay isknown as propagation delay and it must be taken into account in manycircuit designs.1. Connect the circuit in Figure 19. Notice that the output appears toalways be a logic `1' regardless of the input setting.Figure 19zxEE 3714 Logic Gates52. Connect the 1 Mhz digital clock output on the test box to the input ofthe circuit. Monitor the input to the circuit on CH1 of the scope andmonitor the output of the circuit on CH2. Adjust the CH2 verticalscale in order to clearly see the `glitch' caused by propagation delay.Record all waveforms.III. Report………………………………………………………………………………………………………A. Include Section II.B. Explain why a logic `1' can be used as one input to aNAND gate in order to use the gate as an inverter.B. Include Section II.C.C. Include Section II.E. Include accurate drawings of the waveforms.Explain these results.EE 3714 Logic Gates6PRE LAB DATA SHEET (THIS MUST BE FILLED OUT PRIOR TO LAB!!!)TA CHECK OFF SIGNATURE:_______________________________A.1 Explain the concept of Tplh, Tphl. Draw a diagram to illustrate your point:A.2 Gate Delay values:Gate Tplh Tphl74ls0074ls0274ls0874ls3274ls86(case 1)74ls86(case 2)Explanation of 74ls86 delay values (Draw diagrams to illustrate your point).EE 3714 Logic Gates7A.3Gate Voltage ValuesVOH VOL VIH VIL7400VOH – VIH = ____________________VOL – VIL = _____________________Explanation of NOISE MARGIN:Truth Tables:Input Output of FigureA b 3.1 3.2 3.3 3.4 3.5 3.8 3.9 3.10 3.110 00 11 01 1Input Output of FigureX 3.6 3.7 3.1901EE 3714 Logic Gates8Input Output of Figurea b c d 3.12 3.13 3.14 3.150 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1Input Output of Figurea b c 3.16 3.17 3.180 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1LAB DATA SHEET (Record these values during lab!!!)Truth Tables: TA CHECKOFF SIGNATURE: ___________Input Output of FigureA b 3.1 3.2 3.3 3.4 3.5 3.8 3.9 3.10 3.110 00 11 01 1Input Output of FigureX 3.6 3.701Equivalent Gates: 3.9 = ___________, 3.10 = __________, 3.11 = __________Does figures (12,13) & (14,15) have the same results? __________Input Output of Figurea b c 3.16 3.17 3.180 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Input x Figure 3.1901(E) 1. Complete the circuit and obtain the logic result.2. Use the 1 Mhz Clock as input to circuit figure 3.193. Connect CH1 to the input and CH2 to the output. Sketch both the input andoutput waveforms showing the propagation delay, period, pulse-width and